Cypress CY7C0853AV, CY7C0851AV, CY7C0850AV, CY7C0852AV User Manual
FLEx36™ 3.3V 32K/64K/128K/256K x 36
Synchronous Dual-Port RAM
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Features
Functional Description
■ True dual-ported memory cells that allow simultaneous access
of the same memory location
■ Synchronous pipelined operation
■ Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices
■ Pipelined output mode allows fast operation
■ 0.18-micron CMOS for optimum speed and power
■ High-speed clock to data access
■ 3.3V low power
❐ Active as low as 225 mA (typ)
❐ Standby as low as 55 mA (typ)
■ Mailbox function for message passing
■ Global master reset
■ Separate byte enables on both ports
■ Commercial and industrial temperature ranges
■ IEEE 1149.1-compatible JTAG boundary scan
■ 172-Ball FBGA (1 mm pitch) (15 mm × 15 mm)
■ 176-Pin TQFP (24 mm × 24 mm × 1.4 mm)
■ Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
■ Counter readback on address lines
■ Mask register readback on address lines
■ Dual Chip Enables on both ports for easy depth expansion
The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,
synchronous, true dual-port static RAMs that are high-speed,
low-power 3.3V CMOS. Two ports are provided, permitting
independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port
at the same time is undefined. Registers on control, address, and
data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W
input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST
).
The CY7C0853AV device in this family has limited features.
Please see See “Address Counter and Mask Register
Operations” on page 8. for details.
)
Table 1. Product Selection Guide
Density
1-Mbit
(32K x 36)
2-Mbit
(64K x 36)
4-Mbit
(128K x 36)
9-Mbit
(256K x 36)
Part Number CY7C0850AV CY7C0851AV CY7C0852AV CY7C0853AV
Max. Speed (MHz) 167 167 167 133
Max. Access Time - Clock to Data (ns) 4.0 4.0 4.0 4.7
Typical operating current (mA) 225 225 225 270
Package 176TQFP
172FBGA
176TQFP
172FBGA
176TQFP
172FBGA
172FBGA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06070 Rev. *H Revised July 29, 2008
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Logic Block Diagram
A0L–A
17L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
True
RAM Array
18
Addr.
Read
Back
CNTINT
L
Mask Register
Counter/
Address
Register
CNT/MSK
L
Address
Decode
Dual-Ported
Interrupt
Logic
INT
L
Reset
Logic
JTAG
TDO
TMS
TCK
TDI
MRST
DQ9L–DQ
17L
DQ0L–DQ
8L
I/O
Control
9
9
9
9
DQ
18L
–DQ
26L
DQ
27L
–DQ
35L
CE
0L
CE
1L
R/W
L
B0
L
B1
L
B2
L
B3
L
OE
L
A0R–A
17R
CLK
R
ADS
CNTEN
CNTRST
R
18
Addr.
Read
Back
CNTINT
R
Mask Register
Counter/
Address
Register
CNT/MSK
R
Address
Decode
Interrupt
Logic
INT
R
DQ9R–DQ
17R
DQ0R–DQ
8R
I/O
Control
9
9
9
9
DQ
18R
–DQ
26R
DQ
27R
–DQ
35R
CE
0R
CE
1R
R/W
R
B0
R
B1
R
B2
R
B3
R
OE
R
Mirror Reg
Mirror Reg
Note
1. 9M device has 18 address bits, 4M device has 17 address bits, 2M device has 16 address bits, and 1M device has 15 address bits.
[1]
Document #: 38-06070 Rev. *H Page 2 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Pin Configurations
1234567891011121314
A
DQ32L DQ30L CNTINTL VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS CNTINTR DQ30R DQ32R
B
A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
C
NC A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R NC
D
A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R
E
A4L A5L CE1L B0L VDD VSS VDD VDD B0R CE1R A5R A4R
F
VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD
G
OEL B2L B3L CE0L
CY7C0850AV
CY7C0851AV
CY7C0852AV
CE0R B3R B2R OER
H
VSS R/WLA8LCLKL CLKR A8R R/WR VSS
J
A9L A10L VSS ADSL VSS VDD ADSR MRST A10R A9R
K
A11L A12L A15L
[2]
CNTRSTL VDD VDD VSS VDD CNTRSTR A15R
[2]
A12R A11R
L
CNT/MSKL A13L CNTENL DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R CNTENR A13R CNT/MSKR
M
A16L
[2]
A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R
[2]
N
DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
P
DQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R
Note
2. For CY7C0851AV, pins M1 and M14 are NC. For CY7C0850AV, pins K3, K12 M1, and M14 are NC
Figure 1. 172-Ball BGA (Top View)
Document #: 38-06070 Rev. *H Page 3 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Pin Configurations (continued)
1234567891011121314
A
DQ32L DQ30L NC VSS DQ13L VDD DQ11L DQ11R VDD DQ13R VSS NC DQ30R DQ32R
B
A0L DQ33L DQ29L DQ17L DQ14L DQ12L DQ9L DQ9R DQ12R DQ14R DQ17R DQ29R DQ33R A0R
C
A17L A1L DQ31L DQ27L INTL DQ15L DQ10L DQ10R DQ15R INTR DQ27R DQ31R A1R A17R
D
A2L A3L DQ35L DQ34L DQ28L DQ16L VSS VSS DQ16R DQ28R DQ34R DQ35R A3R A2R
E
A4L A5L VDD B0L VDD VSS VDD VDD B0R VDD A5R A4R
F
VDD A6L A7L B1L VDD VSS B1R A7R A6R VDD
G
OEL B2L B3L VSS
CY7C0853AV
VSS B3R B2R OER
H
VSS R/WL A8L CLKL CLKR A8R R/WRVSS
J
A9L A10L VSS VSS VSS VDD VSS MRST A10R A9R
K
A11L A12L A15L VDD VDD VDD VSS VDD VDD A15R A12R A11R
L
VDD A13L VSS DQ26L DQ25L DQ19L VSS VSS DQ19R DQ25R DQ26R VSS A13R VDD
M
A16L A14L DQ22L DQ18L TDI DQ7L DQ2L DQ2R DQ7R TCK DQ18R DQ22R A14R A16R
N
DQ24L DQ20L DQ8L DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R DQ5R DQ6R DQ8R DQ20R DQ24R
P
DQ23L DQ21L TDO VSS DQ4L VDD DQ1L DQ1R VDD DQ4R VSS TMS DQ21R DQ23R
Figure 2.
172-Ball BGA (Top View)
Document #: 38-06070 Rev. *H Page 4 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Pin Configurations (continued)
132
131
130
129
128
127
126
125
124
123
122
104
121
120
119
118
117
116
115
114
113
112
111
110
109
103
108
107
106
105
NC
A
6R
A
5R
A
4R
V
DD
V
SS
DQ
35R
DQ
34R
A
1R
A
2R
A
3R
A
0R
A
7R
B
0R
B
1R
CE
1R
B
2R
B
3R
OE
R
CE
0R
V
DD
V
DD
V
SS
V
SS
R/W
R
CLK
R
MRST
ADS
R
CNTEN
R
A
8R
CNTRST
R
CNT/MSK
R
A
9R
A
10R
A
11R
A
12R
V
SS
V
DD
A
13R
A
14R
A
15R
[2]
A
16R
[2]
DQ
24R
DQ
20R
NC
A
6L
A
5L
A
4L
V
DD
V
SS
DQ
35L
DQ
34L
A
1L
A
2L
A
3L
A
0L
A
7L
B
0L
B
1L
CE
1L
B
2L
B
3L
OE
L
CE
0L
V
DD
V
DD
V
SS
V
SS
R/W
L
CLK
L
V
SS
ADS
L
CNTEN
L
A
8L
CNTRST
L
CNT/MSK
L
A
9L
A
10L
A
11L
A
12L
V
SS
V
DD
A
13L
A
14L
A
15L
[2]
A
16L
[2]
DQ
24L
DQ
20L
DQ
33L
DQ
32L
DQ
31L
V
DD
V
SS
DQ
30L
DQ
28L
DQ
29L
DQ
27L
INT
L
CNTINT
L
DQ
16L
DQ
15L
DQ
17L
DQ
14L
DQ
13L
V
SS
V
DD
DQ
12L
DQ
11L
DQ
10L
DQ
9L
DQ
9R
DQ
10R
DQ
11R
DQ
12R
V
DD
V
SS
DQ
13R
DQ
14R
DQ
17R
DQ
15R
DQ
16R
CNTINT
R
INT
R
DQ
27R
DQ
29R
DQ
28R
DQ
30R
V
SS
V
DD
DQ
31R
DQ
32R
DQ
33R
DQ
26L
DQ
23L
DQ
22L
V
DD
V
SS
DQ
21L
DQ
25L
DQ
19L
DQ
18L
TDI
TDO
DQ
8L
DQ
7L
DQ
6L
DQ
5L
DQ
4L
V
SS
V
DD
DQ
3L
DQ
2L
DQ
1L
DQ
0L
DQ
0R
DQ
1R
DQ
2R
DQ
3R
V
DD
V
SS
DQ
4R
DQ
5R
DQ
6R
DQ
7R
DQ
8R
TMS
TCK
DQ
18R
DQ
19R
DQ
25R
DQ
21R
V
SS
V
DD
DQ
22R
DQ
23R
DQ
26R
102
91
101
100
99
98
97
96
90
95
94
93
92
89
1
2
3
4
5
6
7
8
9
10
11
29
12
13
14
15
16
17
18
19
20
21
22
23
24
30
25
26
27
28
31
42
32
33
34
35
36
37
43
38
39
40
41
44
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
727374
75
76
77
78
79
80
81
82
83
84
85
86
87
88
CY7C0850AV
CY7C0851AV
CY7C0852AV
Figure 3. 176-Pin Thin Quad Flat Pack (TQFP) (Top View)
Document #: 38-06070 Rev. *H Page 5 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Pin Definitions
Note
3. These pins are not available for CY7C0853AV device.
Left Port Right Port Description
A
0L–A17L
[3]
ADS
L
[3]
CE0
L
[3]
CE1
L
CLK
L
CNTEN
L
CNTRST
CNT/MSK
–DQ
DQ
0L
OE
L
[1]
[3]
[3]
L
L
35L
[3]
A0R–A
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ0R–DQ
OE
INTLINTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper
CNTINT
R/W
L
B
0L–B3L
[3]
L
CNTINT
R/W
B0R–B
MRST
TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
TDI JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK JTAG Test Clock Input.
TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
V
SS
V
DD
[1]
17R
[3]
R
Address Inputs.
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
[3]
R
[3]
R
R
[3]
R
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Clock Signal. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS
or CNTRST are
asserted LOW.
[3]
R
R
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst
address counter of its respective port. CNTRST
[3]
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
is not disabled by asserting ADS or CNTEN.
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
Data Bus Input/Output.
35R
R
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
two memory locations can be used for message passing. INT
port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
is asserted LOW when the right
L
deasserted HIGH when it reads the contents of its mailbox.
[3]
R
R
3R
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all “1s.”
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST
LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
machine transitions occur on the rising edge of TCK.
three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Power Inputs.
Document #: 38-06070 Rev. *H Page 6 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Master Reset
Notes
4. CE
is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
5. OE
is “Don’t Care” for mailbox operation.
6. At least one of B0
, B1, B2, or B3 must be LOW.
7. A16x is a NC for CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF; A16x and A15x are NC for CY7C0850AV, therefore the Interrupt Addresses
are 7FFF and 6FFF.
8. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
9. Counter operation and mask register operation is independent of chip enables.
The FLEx36 family devices undergo a complete reset by taking
its MRST
nously to the clocks. The MRST
counters to zero, and the counter mask registers to all ones
(completely unmasked). The MRST
Interrupt (INT
HIGH. The MRST
devices after power up.
input LOW. The MRST input can switch asynchro-
initializes the internal burst
also forces the Mailbox
) flags and the Counter Interrupt (CNTINT) flags
must be performed on the FLEx36 family
in order to set the INT
address 3FFFF asserts INT
active for a Write to generate an interrupt. A valid Read of the
3FFFF location by the right port resets INT
byte has to be active in order for a Read to reset the interrupt.
When one port Writes to the other port’s mailbox, the INT of the
port that the mailbox belongs to is asserted LOW. The INT
reset when the owner (port) of the mailbox Reads the contents
of the mailbox. The interrupt flag is set in a flow-thru mode (i.e.,
it follows the clock edge of the writing port). Also, the flag is reset
flag, a Write operation by the left port to
R
LOW. At least one byte has to be
R
HIGH. At least one
R
in a flow-thru mode (i.e., it follows the clock edge of the reading
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0853AV.
The highest memory location, 3FFFF is the mailbox for the right
port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT
pins should be left open.
port and 3FFFE is the mailbox for the left port. Ta bl e 2 shows that
L
[1, 4, 5, 6, 7]
CE
L
Left Port Right Port
A
0L–17L
INT
R/W
L
CE
R
R
A
0R–17R
INT
Table 2. Interrupt Operation Example
Function
R/W
Set Right INTR Flag L L 3FFFF X X X X L
Reset Right INTR Flag X X X X H L 3FFFF H
Set Left INTL Flag X X X L L L 3FFFE X
Reset Left INTL Flag H L 3FFFE H X X X X
is
R
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)
[8, 9]
CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description
X L X X X X Master Reset Reset address counter to all 0s and mask
register to all 1s.
H H L X X Counter Reset Reset counter unmasked portion to all 0s.
H H H L L Counter Load Load counter with external address value
presented on address lines.
H H H L H Counter Readback Read out counter internal value on address
lines.
H H H H L Counter Increment Internally increment address counter value.
H H H H H Counter Hold Constantly hold the address value for
multiple clock cycles.
H L L X X Mask Reset Reset mask register to all 1s.
H L H L L Mask Load Load mask register with value presented on
the address lines.
H L H L H Mask Readback Read out mask register value on address
lines.
H L H H X Reserved Operation undefined
Document #: 38-06070 Rev. *H Page 7 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Address Counter and Mask Register
Notes
10. This section describes the CY7C0852AV, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851AV has 16 address bits, register lengths
of 16 bits, and a maximum address value of FFFF. The CY7C0850AV has 15 address bits, register lengths of 15 bits, and a maximum address value of 7FFF.
11. CNTINT
and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Operations
This section
CY7C0850AV/CY7C0851AV/CY7C0852AV devices, but not to
the CY7C0853AV device. Each port of these devices has a
programmable burst address counter. The burst counter
contains three registers: a counter register, a mask register, and
a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT
the Mask Load and Mask Reset operations, and by the MRST
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more “0s” in the most significant bits define the masked region,
one or more “1s” in the least significant bits define the unmasked
region. Bit 0 may also be “0,” masking the least significant
counter bit and causing the counter to increment by two instead
of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load operation, and by the MRST
Table 3 on page 7 summarizes the operation of these registers
and the required input control signals. The MRST
is asynchronous. All the other control signals in Table 3 on page
7 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS
port’s CNTEN
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This will Read/Write one word from/into
each successive address location until CNTEN
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST
unmasked portion of the burst counter to 0s. A counter-mask
register is used to control the counter wrap.
Counter Reset Operation
All unmasked bits of the counter are reset to “0.” All masked bits
remain unchanged. The mirror register is loaded with the value
of the burst counter. A Mask Reset followed by a Counter Reset
[10]
describes the features only apply to
) operations.
). The mask register is changed only by
control signal
) and CNTEN signals are LOW. When the
is asserted and the ADS is deasserted, the
is deasserted.
) is used to reset the
will reset the counter and mirror registers to 00000, as will master
reset (MRST
).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0
data lines (DQs) is three-stated. Figure 4 on page 10 shows a
block diagram of the operation.
LOW and CE1 HIGH), the
Counter Increment Operation
Once the address counter register is initially loaded with an
.
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a “1” for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are “1,” the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being “1s,” a counter interrupt flag
(CNTINT
register to its initial value, which was stored in the mirror register.
.
The counter address can instead be forced to loop to 00000 by
externally connecting CNTINT
results in one or more of the unmasked bits of the counter being
“0” deasserts the counter interrupt flag. The example in Figure 5
on page 11 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB
and bit “16” as the MSB. The maximum value the mask register
can be loaded with is 1FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
once the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value till it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT
its maximum value.
) is asserted. The next Increment returns the counter
to CNTRST.
is issued when the counter reaches
[11]
An increment that
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
CA2
Document #: 38-06070 Rev. *H Page 8 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST
.
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal “mirror register” is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this “mirror
register.” If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the “mirror register.” Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit of
the counter. Master reset (MRST
to all “1s.”
) also resets the mask register
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,
003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0
data lines (DQs) is three-stated. Figure 4 on page 10 shows a
block diagram of the operation.
LOW and CE1 HIGH), the
CM2
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0850AV/CY7C0851AV/CY7C0852AV as a 72-bit single
port SRAM in which the counter of one port counts even
addresses and the counter of the other port counts odd
addresses. This even-odd address scheme stores one half of the
72-bit data in even memory locations, and the other half in odd
memory locations.
Document #: 38-06070 Rev. *H Page 9 of 32
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CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
From
Mask
Register
Mirror Counter
Address
Decode
RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To
Counter
Bit 0
Wrap
17 17
17
17
17
1
0
Load/Increment
CNT/MSK
CNTEN
ADS
CNTRST
CLK
Decode
Logic
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
From
Address
Lines
To Readback
and Address
Decode
17
17
MRST
Figure 4. Counter, Mask, and Mirror Logic Block Diagram
[1]
Document #: 38-06070 Rev. *H Page 10 of 32
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