Cypress CY7C0833AV, CY7C0832BV, CY7C0832AV, CY7C0831AV, CY7C0830AV User Manual
...
FLEx18™ 3.3V 64K/128K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Features
Note
1. CY7C0832AV and CY7C0832BV are functionally identical.
■
True Dual-Ported Memory Cells that Allow Simultaneous
Access of the Same Memory Location
■
Synchronous Pipelined Operation
■
Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices
■
Pipelined Output Mode Allows Fast Operation
■
0.18 micron CMOS for Optimum Speed and Power
■
High Speed Clock to Data Access
■
3.3V Low Power
❐
Active as Low as 225 mA (typ)
❐
Standby as Low as 55 mA (typ)
■
Mailbox Function for Message Passing
■
Global Master Reset
■
Separate Byte Enables on Both Ports
■
Commercial and Industrial Temperature Ranges
■
IEEE 1 149.1 Comp atible JTAG Boundary Scan
■
144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
■
120 TQFP (14 mm x 14 mm x 1.4 mm)
■
Pb-Free Packages Available
■
Counter Wrap Around Control
❐
Internal Mask Register Controls Counter Wrap Around
❐
Counter-Interrupt Flags to Indicate Wrap Around
❐
Memory Block Retransmit Operation
■
Counter Readback on Address Lines
■
Mask Register Readback on Address Lines
■
Dual Chip Enables on Both Ports for Easy Depth Expansion
Functional Description
The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location by
more than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal setup and hold
time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST
).
The CY7C0833AV device in this family has limited features. See
Address Counter and Mask Register Operations
for details.
input signal. The internal Write pulse
[16]
on page 6
Table 1. Product Selection Guide
Density
512 Kbit
(32K x 18)
Part Number CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0832BV
1 Mbit
(64K x 18)
2 Mbit
(128K x 18)
4 Mbit
(256K x 18)
(512K x 18)
[1]
CY7C0833AV
9 Mbit
Maximum Speed (MHz) 167 167 167 167 133 133
Maximum Access Time -
4.0 4.0 4.0 4.0 4.4 4.7
Clock to Data (ns)
Typical Operating
225 225 225 225 225 270
Current (mA)
Package 144 FBGA 120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP 144 FBGA
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06059 Rev. *S Revised March 03, 2009
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Logic Block Diagram
A0L–A
18L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
True
RAM Array
19
Addr.
Read
Back
CNTINT
L
Mask Register
Counter/
Address
Register
CNT/MSK
L
Address
Decode
Dual-Ported
Interrupt
Logic
INT
L
Reset
Logic
JTAG
TDO
TMS
TCK
TDI
MRST
DQ9L–DQ
17L
DQ0L–DQ
8L
I/O
Control
9
9
CE
0L
CE
1L
R/W
L
B0
L
B1
L
OE
L
A0R–A
18R
CLK
R
ADS
CNTEN
CNTRST
R
19
Addr.
Read
Back
CNTINT
R
Mask Register
Counter/
Address
Register
CNT/MSK
R
Address
Decode
Interrupt
Logic
INT
R
I/O
Control
9
9
CE
0R
CE
1R
R/W
R
B0
R
B1
R
OE
R
Mirror Reg
Mirror Reg
DQ0R–DQ
8R
DQ9R–DQ
17R
Note
2. CY7C0837AV has 15 address bits, CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV/CY7C0832BV has 18 address bits and
CY7C0833AV has 19 address bits.
[2]
Document #: 38-06059 Rev. *S Page 2 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
Notes
3. Leave this ball unconnected for CY7C0837AV.
4. Leave this ball unconnected for CY7C0837AV and CY7C0830AV.
5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV.
6. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV, and CY7C0832AV.
7. These balls are not applicable for CY7C0833A V device. They must be tied to VDD.
8. These balls are not applicable for CY7C0833A V device. They must be tied to VSS.
9. These balls are not applicable for CY7C0833AV device. They must not be connected.
1 2 3 4 5 6 7 8 9 10 11 12
Figure 1. 144-Ball BGA (Top View)
CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV
DQ17
A
A0
B
A2
C
A4
D
A6
E
A8
F
A10
G
A12
H
A14
J
DQ16
L
L
L
L
L
L
L
L
L
A1
A3
A5
A7
A9
A11
A13
A15
[3]
DQ14
L
DQ15
L
L
L
L
L
CE1
[7]
CE0
[8]
B1
C
L
L
L
B0
OE
RW
DQ12
L
DQ13
L
L
L
L
L
L
L
L
INT
NC VDD VDD VDD VDD NC
NC VDD VSS VSS VDD NC B1
NC VSS VSS VSS VSS NC C
NC VSS VSS VSS VSS NC B0
NC VDD VSS VSS VDD NC OE
NC VDD VDD VDD VDD NC RW
DQ10
L
DQ11
L
CNTINT
L
[9]
DQ9
L
MRST NC DQ11
L
ADS
L
[8]
DQ9
L
ADS
L
DQ10
R
CNTINT
R
[8]
[9]
DQ12
R
DQ13
R
R
INT
DQ14
R
DQ15
R
CE1
R
CE
[7]
[8]
R
DQ16
R
A1
R
R
0
R
R
A3
A5
A7
A9
R
R
R
A11
A13
A15
[3]
DQ17
R
R
R
R
R
R
R
R
R
A0
A2
A4
A6
A8
A10
A12
A14
R
R
R
R
R
R
R
R
R
A16
K
[4]
A18
L
[6]
DQ8
M
Document #: 38-06059 Rev. *S Page 3 of 28
A17
L
L
L
[5]
NC DQ6
DQ7
CNT/MSK
L
L
[7]
DQ5
L
TDO
DQ4
L
DQ3
L
CNTRST
L
L
L
TCK TMS
CNTEN
[8]
DQ0
[7]
DQ2
L
DQ1
L
CNTRST
R
[7]
CNTEN
L
L
DQ0
R
DQ2
DQ1
R
R
[8]
R
TDI
DQ4
DQ3
CNT/MSK
[7]
DQ6
R
DQ5
R
A17
R
[5]
R
R
NC
DQ7
A16
R
R
[4]
A18
[6]
DQ8
R
R
R
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
999897969594939291
DQ
11L
CNTINT
L
INTLDQ9LDQ
10LDQ12L
V
SS
VDDDQ
13LDQ14L
DQ
15LDQ16LDQ17L
A0LA
1L
DQ
16R
A1RA0RDQ
17R
DQ
15RDQ14R
DQ
13R
VDDV
SS
DQ
12RDQ11RDQ10RDQ9R
INT
R
CNTINT
R
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
1R
V
SS
V
DD
CE
0R
OE
R
B
0R
CE
1R
A
7R
A
6R
A
5R
A
4R
V
DD
V
SS
A
3R
A
2R
A
12R
A
13R
V
DD
V
SS
A
11R
A
10R
A
9R
A
8R
CNT/MSK
R
CNTRST
R
CNTEN
R
ADS
R
MRST
CLK
R
R/W
R
3132333435363738394041424344454647484950515253545556575859
60
V
SS
DQ0LDQ1LDQ2LDQ
3L
VDDDQ4LDQ5LDQ6LDQ7LDQ8LA
17L
[10]
A
16L
[9]
A
15LA14L
A
17R
[10]
A
14RA15RA16R
[9]
DQ8RDQ7RDQ6RDQ5RDQ4RVDDVSSDQ3RDQ2RDQ1RDQ
0R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
1L
V
SS
V
DD
CE
0L
OE
L
B
0L
A
7L
A
6L
A
5L
A
4L
V
DD
V
SS
A
3L
A
2L
A
12L
A
13L
V
DD
V
SS
A
11L
A
10L
A
9L
A
8L
CNT/MSK
L
CNTRST
L
CNTEN
L
ADS
L
V
SS
CLK
L
R/W
L
CE
1L
Notes
10.Leave this pin unconnected for CY7C0830AV.
11.Leave this pin unconnected for CY7C0830AV and CY7C0831AV.
Figure 2. 120-Pin Thin Quad Flat Pack (TQFP) (Top View)
CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0832BV
Document #: 38-06059 Rev. *S Page 4 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Definitions
Left Port Right Port Description
A
0L–A18L
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ
OE
INT
CNTINT
R/W
B0L–B
[2]
[8]
L
[8]
L
[7]
L
L
[8]
L
[7]
L
L
–DQ
0L
17L
L
LINTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
[9]
L
L
1L
[7]
A0R–A
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ0R–DQ
OE
CNTINT
R/W
B0R–B
MRST
TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
TDI JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK JTAG Test Clock Input.
TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
V
SS
V
DD
[2]
18R
[8]
R
Address Inputs.
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
[8]
R
[7]
R
R
[8]
R
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Clock Signal. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS
or CNTRST are
asserted LOW.
[7]
R
R
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST
CNTEN
[7]
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
.
is not disabled by asserting ADS or
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
17R
R
Data Bus Input/Output .
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
upper two memory locations are used for message passing. INT
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
is asserted LOW when the
L
deasserted HIGH when it reads the contents of its mailbox.
[9]
R
R
1R
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST
LOW performs all of the reset functions as describ e d in th e te xt. A M RST operation is
required at power up.
machine transitions occur on the rising edge of TCK.
three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Power Inputs.
Byte Select Operation
Control Pin Effect
DQ
DQ
0–8
9–17
Byte Control
Byte Control
B
0
B
1
Document #: 38-06059 Rev. *S Page 5 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Master Reset
Notes
12.CE
is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out aft er the following CLK edge and is three-stated after the next CLK edge.
13.OE
is “Don’t Care” for mailbox operation.
14.At least one of BE0
, BE1 must be LOW.
15.A18x is a NC for CY7C0832AV/CY7C0832BV, therefore the I nterrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC f or CY7C0831A V, therefore the Interrupt
addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830A V, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x an d A15x
are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE.
16.This section describes the CY7C0832AV/CY7C0832BV, CY7C0831AV, CY7C0830AV and CY7C0837AV having 18, 17, 16 and 15 address bits.
17.“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
The FLEx18 family devices undergo a complete reset by taking
its MRST
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT
MRST
power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0833AV.
The highest memory location, 7FFFF is the mailbox for the right
port and 7FFFE is the mailbox for the left port. Table 2 shows that
to set the INT
7FFFF asserts INT
a Write to generate an interrupt. A valid Read of the 7FFFF
location by the right port resets INTR HIGH. At least one byte
must be active for a Read to reset the interrupt. When one port
Writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW. The INT
owner (port) of the mailbox Reads the contents of the mailbox.
The interrupt flag is set in a flow-through mode (that is, it follows
the clock edge of the writing port). Also, the flag is reset in a
flow-through mode (that is, it follows the clock edge of the
reading port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT
Address Counter and Mask Register Operations
This section describes the features only apply to 512 Kbit,1 Mbit,
2 Mbit, and 4 Mbit devices. It does not apply to 9 Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
T able 2. Interrupt Operation Example
input LOW. The MRST input can switch asynchro-
) flags and the Counter Interrupt (CNTINT) flags HIGH.
must be performed on the FLEx18 family devices after
flag, a Write operation by the left port to address
R
LOW. At least one byte has to be active for
R
is reset when the
pins should be left open.
[16]
[2, 12, 13, 14, 15, 17]
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST
) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT
). The mask register is changed only by
the Mask Load and Mask Reset operations and by the MRST
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more ‘0s’ in the most significant bits define the masked region,
one or more ‘1s’ in the least significant bits define the unmasked
region. Bit 0 may also be ‘0,’ masking the least significant counter
bit and causing the counter to increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see Retransmit on page 8). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and by the MRST
instructions. Table 3 on page 7 summarizes the operation of these
registers and the required input control signals. The MRST
control signal is asynchronous. All the other co ntrol signals in
Table 3 on page 7 (CNT/MSK
, CNTRST, ADS, CNTEN) are
synchronized to the port’s CLK. All these counter and mask
operations are independent of the port’s chip enable inputs (CE0
and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN
is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads and writes one word from and
to each successive address location until CNTEN
s deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to I/0s. A counte r-mask
register is used to control the counter wrap.
.
FUNCTION LEFT PORT RIGHT PORT
R/W
L
CE
A0L–A
L
18L
INT
R/W
L
R
CE
A0R–A
R
18R
Set Right INTR Flag L L 3FFFF X X X X L
Reset Right INT
Set Left INT
Reset Left INT
Set Right INT
Document #: 38-06059 Rev. *S Page 6 of 28
Flag X X X X H L 3FFFF H
R
Flag X X X L L L 3FFFE X
L
Flag H L 3FFFE H X X X X
L
Flag L L 3FFFF X X X X L
R
INT
R
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Counter Reset Operation
All unmasked bits of the counter are reset to ‘0.’ All masked bits
remain unchanged. The mirror register is loaded with the value
of the burst counter. A Mask Reset followed by a Counter Reset
resets the counter and mirror registers to 00000, as does master
reset (MRST
).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
When the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a ‘1’ for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are ‘1,’ the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being ‘1s,’ a counter interrupt flag
(CNTINT
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 00000 by
externally connecting CNTINT
results in one or more of the unmasked bits of the counter being
‘0’ deasserts the counter interrupt flag. The example in Figure 4
on page 10 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit ‘0’ as the LSB
and bit ‘16’ as the MSB. The maximum value the mask register
can be loaded with is 3FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
Table 3. Address Counter and Counter-Mask Reg i ster Control Operation (Any Port)
CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description
) is asserted. The next Increment returns the counter
to CNTRST .
X L X X X X Master Reset Reset address counter to all 0s and mask
H H L X X Counter Reset Reset counter unmasked portion to all 0s.
[19]
An increment that
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
after the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value until it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT
its maximum value
is issued when the counter reaches
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all ‘1s.’ It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST
.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0
data lines (DQs) are three-stated. Figure 3 on page 9 shows a
block diagram of the operation.
[17, 18]
register to all 1s.
LOW and CE1 HIGH), the
CA2
H H H L L Counter Load Load counter with external address value
presented on address lines.
H H H L H Counter Readback Read out counter internal value on address
lines.
H H H H L Counter Increment Internally increment address counter value.
H H H H H Counter Hold Constantly hold the address value for multiple
clock cycles.
H L L X X Mask Reset Reset mask register to all 1s.
H L H L L Mask Load Load mask register with value presented on
H L H L H M ask R eadback Read out mask register value on address
H L H H X Reserved Operation undefined
Notes
18.Counter operation and mask register operation is independent of chip enables.
19.CNTINT
Document #: 38-06059 Rev. *S Page 7 of 28
and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
the address lines.
lines.
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal mirror register is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this mirror
register. If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the mirror register. Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all ‘1s,’ which unmasks every bit of
the counter. Master reset (MRST
to all ‘1s’.
) also resets the mask register
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment operations. Permitted values are of the form 2
most significant bit to the least significant bit, permitted values
have zero or more ‘0s,’ one or more ‘1s,’ or one ‘0.’ Thus 3FFFF,
003FE, and 00001 are permitted values, but 3F0FF , 003FC, and
00000 are not.
n
– 1 or 2n – 2. From the
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0
data lines (DQs) is three-stated. Figure 3 on page 9 shows a
block diagram of the operation.
LOW and CE1 HIGH), the
CM2
Counting by Two
When the least significant bit of the mask register is ‘0,’ the
counter increments by two. This may be used to connect the x18
devices as a 36-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 36-bit data in even memory locations, and the
other half in odd memory locations.
Document #: 38-06059 Rev. *S Page 8 of 28
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
From
Mask
Register
Mirror Counter
Address
Decode
RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To
Counter
Bit 0
Wrap
17 17
17
17
17
1
0
Load/Increment
CNT/MSK
CNTEN
ADS
CNTRST
CLK
Decode
Logic
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
From
Address
Lines
To Readback
and Address
Decode
17
17
MRST
Figure 3. Counter, Mask, and Mirror Logic Block Diagram
[1]
Document #: 38-06059 Rev. *S Page 9 of 28
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