FLEx18™ 3.3V 64K/128K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Features
Note
1. CY7C0832AV and CY7C0832BV are functionally identical.
■
True Dual-Ported Memory Cells that Allow Simultaneous
Access of the Same Memory Location
■
Synchronous Pipelined Operation
■
Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices
■
Pipelined Output Mode Allows Fast Operation
■
0.18 micron CMOS for Optimum Speed and Power
■
High Speed Clock to Data Access
■
3.3V Low Power
❐
Active as Low as 225 mA (typ)
❐
Standby as Low as 55 mA (typ)
■
Mailbox Function for Message Passing
■
Global Master Reset
■
Separate Byte Enables on Both Ports
■
Commercial and Industrial Temperature Ranges
■
IEEE 1 149.1 Comp atible JTAG Boundary Scan
■
144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
■
120 TQFP (14 mm x 14 mm x 1.4 mm)
■
Pb-Free Packages Available
■
Counter Wrap Around Control
❐
Internal Mask Register Controls Counter Wrap Around
❐
Counter-Interrupt Flags to Indicate Wrap Around
❐
Memory Block Retransmit Operation
■
Counter Readback on Address Lines
■
Mask Register Readback on Address Lines
■
Dual Chip Enables on Both Ports for Easy Depth Expansion
Functional Description
The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location by
more than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal setup and hold
time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST
).
The CY7C0833AV device in this family has limited features. See
Address Counter and Mask Register Operations
for details.
input signal. The internal Write pulse
[16]
on page 6
Table 1. Product Selection Guide
Density
512 Kbit
(32K x 18)
Part Number CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0832BV
1 Mbit
(64K x 18)
2 Mbit
(128K x 18)
4 Mbit
(256K x 18)
(512K x 18)
[1]
CY7C0833AV
9 Mbit
Maximum Speed (MHz) 167 167 167 167 133 133
Maximum Access Time -
4.0 4.0 4.0 4.0 4.4 4.7
Clock to Data (ns)
Typical Operating
225 225 225 225 225 270
Current (mA)
Package 144 FBGA 120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP
144 FBGA
120 TQFP 144 FBGA
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06059 Rev. *S Revised March 03, 2009
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Logic Block Diagram
A0L–A
18L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
True
RAM Array
19
Addr.
Read
Back
CNTINT
L
Mask Register
Counter/
Address
Register
CNT/MSK
L
Address
Decode
Dual-Ported
Interrupt
Logic
INT
L
Reset
Logic
JTAG
TDO
TMS
TCK
TDI
MRST
DQ9L–DQ
17L
DQ0L–DQ
8L
I/O
Control
9
9
CE
0L
CE
1L
R/W
L
B0
L
B1
L
OE
L
A0R–A
18R
CLK
R
ADS
CNTEN
CNTRST
R
19
Addr.
Read
Back
CNTINT
R
Mask Register
Counter/
Address
Register
CNT/MSK
R
Address
Decode
Interrupt
Logic
INT
R
I/O
Control
9
9
CE
0R
CE
1R
R/W
R
B0
R
B1
R
OE
R
Mirror Reg
Mirror Reg
DQ0R–DQ
8R
DQ9R–DQ
17R
Note
2. CY7C0837AV has 15 address bits, CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV/CY7C0832BV has 18 address bits and
CY7C0833AV has 19 address bits.
[2]
Document #: 38-06059 Rev. *S Page 2 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
Notes
3. Leave this ball unconnected for CY7C0837AV.
4. Leave this ball unconnected for CY7C0837AV and CY7C0830AV.
5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV.
6. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV, and CY7C0832AV.
7. These balls are not applicable for CY7C0833A V device. They must be tied to VDD.
8. These balls are not applicable for CY7C0833A V device. They must be tied to VSS.
9. These balls are not applicable for CY7C0833AV device. They must not be connected.
1 2 3 4 5 6 7 8 9 10 11 12
Figure 1. 144-Ball BGA (Top View)
CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV
DQ17
A
A0
B
A2
C
A4
D
A6
E
A8
F
A10
G
A12
H
A14
J
DQ16
L
L
L
L
L
L
L
L
L
A1
A3
A5
A7
A9
A11
A13
A15
[3]
DQ14
L
DQ15
L
L
L
L
L
CE1
[7]
CE0
[8]
B1
C
L
L
L
B0
OE
RW
DQ12
L
DQ13
L
L
L
L
L
L
L
L
INT
NC VDD VDD VDD VDD NC
NC VDD VSS VSS VDD NC B1
NC VSS VSS VSS VSS NC C
NC VSS VSS VSS VSS NC B0
NC VDD VSS VSS VDD NC OE
NC VDD VDD VDD VDD NC RW
DQ10
L
DQ11
L
CNTINT
L
[9]
DQ9
L
MRST NC DQ11
L
ADS
L
[8]
DQ9
L
ADS
L
DQ10
R
CNTINT
R
[8]
[9]
DQ12
R
DQ13
R
R
INT
DQ14
R
DQ15
R
CE1
R
CE
[7]
[8]
R
DQ16
R
A1
R
R
0
R
R
A3
A5
A7
A9
R
R
R
A11
A13
A15
[3]
DQ17
R
R
R
R
R
R
R
R
R
A0
A2
A4
A6
A8
A10
A12
A14
R
R
R
R
R
R
R
R
R
A16
K
[4]
A18
L
[6]
DQ8
M
Document #: 38-06059 Rev. *S Page 3 of 28
A17
L
L
L
[5]
NC DQ6
DQ7
CNT/MSK
L
L
[7]
DQ5
L
TDO
DQ4
L
DQ3
L
CNTRST
L
L
L
TCK TMS
CNTEN
[8]
DQ0
[7]
DQ2
L
DQ1
L
CNTRST
R
[7]
CNTEN
L
L
DQ0
R
DQ2
DQ1
R
R
[8]
R
TDI
DQ4
DQ3
CNT/MSK
[7]
DQ6
R
DQ5
R
A17
R
[5]
R
R
NC
DQ7
A16
R
R
[4]
A18
[6]
DQ8
R
R
R
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
999897969594939291
DQ
11L
CNTINT
L
INTLDQ9LDQ
10LDQ12L
V
SS
VDDDQ
13LDQ14L
DQ
15LDQ16LDQ17L
A0LA
1L
DQ
16R
A1RA0RDQ
17R
DQ
15RDQ14R
DQ
13R
VDDV
SS
DQ
12RDQ11RDQ10RDQ9R
INT
R
CNTINT
R
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
1R
V
SS
V
DD
CE
0R
OE
R
B
0R
CE
1R
A
7R
A
6R
A
5R
A
4R
V
DD
V
SS
A
3R
A
2R
A
12R
A
13R
V
DD
V
SS
A
11R
A
10R
A
9R
A
8R
CNT/MSK
R
CNTRST
R
CNTEN
R
ADS
R
MRST
CLK
R
R/W
R
3132333435363738394041424344454647484950515253545556575859
60
V
SS
DQ0LDQ1LDQ2LDQ
3L
VDDDQ4LDQ5LDQ6LDQ7LDQ8LA
17L
[10]
A
16L
[9]
A
15LA14L
A
17R
[10]
A
14RA15RA16R
[9]
DQ8RDQ7RDQ6RDQ5RDQ4RVDDVSSDQ3RDQ2RDQ1RDQ
0R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
1L
V
SS
V
DD
CE
0L
OE
L
B
0L
A
7L
A
6L
A
5L
A
4L
V
DD
V
SS
A
3L
A
2L
A
12L
A
13L
V
DD
V
SS
A
11L
A
10L
A
9L
A
8L
CNT/MSK
L
CNTRST
L
CNTEN
L
ADS
L
V
SS
CLK
L
R/W
L
CE
1L
Notes
10.Leave this pin unconnected for CY7C0830AV.
11.Leave this pin unconnected for CY7C0830AV and CY7C0831AV.
Figure 2. 120-Pin Thin Quad Flat Pack (TQFP) (Top View)
CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0832BV
Document #: 38-06059 Rev. *S Page 4 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Definitions
Left Port Right Port Description
A
0L–A18L
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ
OE
INT
CNTINT
R/W
B0L–B
[2]
[8]
L
[8]
L
[7]
L
L
[8]
L
[7]
L
L
–DQ
0L
17L
L
LINTR Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
[9]
L
L
1L
[7]
A0R–A
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ0R–DQ
OE
CNTINT
R/W
B0R–B
MRST
TMS JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
TDI JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK JTAG Test Clock Input.
TDO JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
V
SS
V
DD
[2]
18R
[8]
R
Address Inputs.
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
[8]
R
[7]
R
R
[8]
R
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Clock Signal. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS
or CNTRST are
asserted LOW.
[7]
R
R
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST
CNTEN
[7]
Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to
.
is not disabled by asserting ADS or
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
17R
R
Data Bus Input/Output .
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
upper two memory locations are used for message passing. INT
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
is asserted LOW when the
L
deasserted HIGH when it reads the contents of its mailbox.
[9]
R
R
1R
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
Byte Select Inputs. Asserting these signals enables Read and Write operations to the corresponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting
MRST
LOW performs all of the reset functions as describ e d in th e te xt. A M RST operation is
required at power up.
machine transitions occur on the rising edge of TCK.
three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Power Inputs.
Byte Select Operation
Control Pin Effect
DQ
DQ
0–8
9–17
Byte Control
Byte Control
B
0
B
1
Document #: 38-06059 Rev. *S Page 5 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Master Reset
Notes
12.CE
is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out aft er the following CLK edge and is three-stated after the next CLK edge.
13.OE
is “Don’t Care” for mailbox operation.
14.At least one of BE0
, BE1 must be LOW.
15.A18x is a NC for CY7C0832AV/CY7C0832BV, therefore the I nterrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC f or CY7C0831A V, therefore the Interrupt
addresses are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CY7C0830A V, therefore the Interrupt Addresses are FFFF and FFFE;A18x, A17x, A16x an d A15x
are NC for CY7C0837AV, therefore the Interrupt Addresses are 7FFF and 7FFE.
16.This section describes the CY7C0832AV/CY7C0832BV, CY7C0831AV, CY7C0830AV and CY7C0837AV having 18, 17, 16 and 15 address bits.
17.“X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
The FLEx18 family devices undergo a complete reset by taking
its MRST
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT
MRST
power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CY7C0833AV.
The highest memory location, 7FFFF is the mailbox for the right
port and 7FFFE is the mailbox for the left port. Table 2 shows that
to set the INT
7FFFF asserts INT
a Write to generate an interrupt. A valid Read of the 7FFFF
location by the right port resets INTR HIGH. At least one byte
must be active for a Read to reset the interrupt. When one port
Writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW. The INT
owner (port) of the mailbox Reads the contents of the mailbox.
The interrupt flag is set in a flow-through mode (that is, it follows
the clock edge of the writing port). Also, the flag is reset in a
flow-through mode (that is, it follows the clock edge of the
reading port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT
Address Counter and Mask Register Operations
This section describes the features only apply to 512 Kbit,1 Mbit,
2 Mbit, and 4 Mbit devices. It does not apply to 9 Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
T able 2. Interrupt Operation Example
input LOW. The MRST input can switch asynchro-
) flags and the Counter Interrupt (CNTINT) flags HIGH.
must be performed on the FLEx18 family devices after
flag, a Write operation by the left port to address
R
LOW. At least one byte has to be active for
R
is reset when the
pins should be left open.
[16]
[2, 12, 13, 14, 15, 17]
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST
) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT
). The mask register is changed only by
the Mask Load and Mask Reset operations and by the MRST
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more ‘0s’ in the most significant bits define the masked region,
one or more ‘1s’ in the least significant bits define the unmasked
region. Bit 0 may also be ‘0,’ masking the least significant counter
bit and causing the counter to increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see Retransmit on page 8). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and by the MRST
instructions. Table 3 on page 7 summarizes the operation of these
registers and the required input control signals. The MRST
control signal is asynchronous. All the other co ntrol signals in
Table 3 on page 7 (CNT/MSK
, CNTRST, ADS, CNTEN) are
synchronized to the port’s CLK. All these counter and mask
operations are independent of the port’s chip enable inputs (CE0
and CE1).
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN
is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This reads and writes one word from and
to each successive address location until CNTEN
s deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to I/0s. A counte r-mask
register is used to control the counter wrap.
.
FUNCTION LEFT PORT RIGHT PORT
R/W
L
CE
A0L–A
L
18L
INT
R/W
L
R
CE
A0R–A
R
18R
Set Right INTR Flag L L 3FFFF X X X X L
Reset Right INT
Set Left INT
Reset Left INT
Set Right INT
Document #: 38-06059 Rev. *S Page 6 of 28
Flag X X X X H L 3FFFF H
R
Flag X X X L L L 3FFFE X
L
Flag H L 3FFFE H X X X X
L
Flag L L 3FFFF X X X X L
R
INT
R
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Counter Reset Operation
All unmasked bits of the counter are reset to ‘0.’ All masked bits
remain unchanged. The mirror register is loaded with the value
of the burst counter. A Mask Reset followed by a Counter Reset
resets the counter and mirror registers to 00000, as does master
reset (MRST
).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
When the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a ‘1’ for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are ‘1,’ the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being ‘1s,’ a counter interrupt flag
(CNTINT
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 00000 by
externally connecting CNTINT
results in one or more of the unmasked bits of the counter being
‘0’ deasserts the counter interrupt flag. The example in Figure 4
on page 10 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit ‘0’ as the LSB
and bit ‘16’ as the MSB. The maximum value the mask register
can be loaded with is 3FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
Table 3. Address Counter and Counter-Mask Reg i ster Control Operation (Any Port)
CLK MRST CNT/MSK CNTRST ADS CNTEN Operation Description
) is asserted. The next Increment returns the counter
to CNTRST .
X L X X X X Master Reset Reset address counter to all 0s and mask
H H L X X Counter Reset Reset counter unmasked portion to all 0s.
[19]
An increment that
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
after the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value until it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT
its maximum value
is issued when the counter reaches
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all ‘1s.’ It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST
.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0
data lines (DQs) are three-stated. Figure 3 on page 9 shows a
block diagram of the operation.
[17, 18]
register to all 1s.
LOW and CE1 HIGH), the
CA2
H H H L L Counter Load Load counter with external address value
presented on address lines.
H H H L H Counter Readback Read out counter internal value on address
lines.
H H H H L Counter Increment Internally increment address counter value.
H H H H H Counter Hold Constantly hold the address value for multiple
clock cycles.
H L L X X Mask Reset Reset mask register to all 1s.
H L H L L Mask Load Load mask register with value presented on
H L H L H M ask R eadback Read out mask register value on address
H L H H X Reserved Operation undefined
Notes
18.Counter operation and mask register operation is independent of chip enables.
19.CNTINT
Document #: 38-06059 Rev. *S Page 7 of 28
and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
the address lines.
lines.
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal mirror register is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this mirror
register. If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the mirror register. Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all ‘1s,’ which unmasks every bit of
the counter. Master reset (MRST
to all ‘1s’.
) also resets the mask register
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment operations. Permitted values are of the form 2
most significant bit to the least significant bit, permitted values
have zero or more ‘0s,’ one or more ‘1s,’ or one ‘0.’ Thus 3FFFF,
003FE, and 00001 are permitted values, but 3F0FF , 003FC, and
00000 are not.
n
– 1 or 2n – 2. From the
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0
data lines (DQs) is three-stated. Figure 3 on page 9 shows a
block diagram of the operation.
LOW and CE1 HIGH), the
CM2
Counting by Two
When the least significant bit of the mask register is ‘0,’ the
counter increments by two. This may be used to connect the x18
devices as a 36-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 36-bit data in even memory locations, and the
other half in odd memory locations.
Document #: 38-06059 Rev. *S Page 8 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
From
Mask
Register
Mirror Counter
Address
Decode
RAM
Array
Wrap
1
0
Increment
Logic
1
0
+1
+2
1
0
Wrap
Detect
From
Mask
From
Counter
To
Counter
Bit 0
Wrap
17 17
17
17
17
1
0
Load/Increment
CNT/MSK
CNTEN
ADS
CNTRST
CLK
Decode
Logic
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
From
Address
Lines
To Readback
and Address
Decode
17
17
MRST
Figure 3. Counter, Mask, and Mirror Logic Block Diagram
[1]
Document #: 38-06059 Rev. *S Page 9 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 4. Programmable Counter-Mask Register Operation
2162
15
2
6
2
1
2
5
2
2
242
3
2
0
2162
15
2
6
2
1
2
5
2
2
242
3
2
0
2162
15
2
6
2
1
2
5
2
2
242
3
2
0
2162
15
2
6
2
1
2
5
2
2
242
3
2
0
H
H
L
H
110s1010101
00Xs1X0X0X0
11Xs1X1X1X1
00Xs1X0X0X0
Masked Address Unmasked Address
Mask
Register
bit-0
Address
Counter
bit-0
CNTINT
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max
Address
Register
Max + 1
Address
Register
Notes
20.The “X” in this diagram represents the counter upper bits
21.Boundary scan is IEEE 1149.1-compatible. See Performing a Pause/Restart on page 10 for deviation from strict 1149.1 compliance
[2, 20]
IEEE 1149.1 Serial Boundary Scan (JTAG)
[21]
The FLEx18 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 compliant TAPs. The TAP operates
using JEDEC-standard 3.3V I/O logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of th e
devices, and may be performed while the device is operating. An
MRST
must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT -DR P AUSE-DR SHIFT -DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outp uts a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
Boundary Scan Hierarchy for 9-Mbit Device
Internally, the CY7C0833A V have two DIEs. Each DIE contain all
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain of
each DIE are connected serially to form the scan chain of the
CY7C0833AV as shown in Figure 5 on page 11 . TMS and TCK
are connected in parallel to each DIE to drive all TAP controllers
in unison. In many cases, each DIE is supplied with the same
instruction. In other cases, it might be useful to supply different
instructions to each DIE. One example would be testing the
device ID of one DIE while bypassing the others.
Each pin of FLEx18 family is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This is accomplished
by merging the netlist of the devices with the netlist of the user’s
circuit board. To facilitate boundary scan testing of the devices,
Cypress provides the BSDL file for each DIE, the internal netlist
of the device, and a description of the device scan chain. The
user can use these materials to easily integrate the devices into
the board’s boundary scan environment. Further information is
found in the Cypress application note Using JTAG Boundary
Scan For System in a Package (SIP) Dual-Port SRAMs.
Document #: 38-06059 Rev. *S Page 10 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Figure 5. Scan Chain for 9 Mb Device
D2
TDO
TDI
D1
TDO
TDI
TDI
TDO
Note
22.See details in the device BSDL file.
Table 4. Identification Register Definitions
Instruction Field Value Description
Revision Number (31:28) 0h Reserved for version number.
Cypress Device ID
Cypress JEDEC ID (11:1) 034h Allows unique identification of the DP family device vendor.
ID Register Presence (0) 1 Indicates the presence of an ID register.
(27:12) C090h Defines Cypress part number for CY7C0832AV/CY7C0832BV
C091h Defines Cypress part number for CY7C0831AV
C093h Defines Cypress part number for CY7C0830AV
C094h Defines Cypress part number for CY7C0837AV.
Table 5. Scan Registers Sizes
Register Name Bit Size
Instruction 4
Bypass 1
Identification 32
Boundary Scan n
T able 6. Instruction Identification Codes
Instruction Code Description
EXTEST 0000 Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS 1111 Places the BYR between TDI and TDO.
IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ 0111 Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
CLAMP 0100 Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000 Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST 1100 Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED All other codes Other combinations are reserved. Do not use other than the above.
[22]
Document #: 38-06059 Rev. *S Page 11 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Maximum Ratings
Notes
23.The voltage on any input or I/O pin can not exceed the power pin during power up.
24.Pulse width < 20 ns.
25.I
SB1
, I
SB2
, I
SB3
and I
SB4
are not applicable for CY7C0833AV because it can not be powered down by using chip enable pins.
26.C
OUT
also references C
I/O
.
Exceeding maximum ratings
device. These user guidelines are not tested.
Storage Temperature................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State.........................–0.5V to V
DC Input Voltage .............................. –0.5V to V
[23]
may impair the useful life of the
+ 0.5V
DD
+ 0.5V
DD
[24]
Electrical Characteristics
Over the Operating Range
Parameter Description
V
V
V
V
I
I
I
I
I
I
I
I
I
OH
OL
IH
IL
OZ
IX1
IX2
CC
SB1
SB2
SB3
SB4
SB5
[25]
[25]
[25]
[25]
Output HIGH Voltage (V
Output LOW Voltage (V
= Min., IOH= –4.0 mA) 2.4 2.4 2.4 V
DD
= Min., IOL= +4.0 mA) 0.4 0.4 0.4 V
DD
Input HIGH Voltage 2.0 2.0 2.0 V
Input LOW Voltage 0.8 0.8 0.8 V
Output Leakage Current –10 10 –10 10 –10 10 μA
Input Leakage Current Except TDI, TMS, MRST –10 10 –10 10 –10 10 μA
Input Leakage Current TDI, TMS, MRST –0.1 1.0 –0.1 1.0 –0.1 1.0 mA
Operating Current for
(V
= Max., I
DD
Disabled
= 0 mA), Outputs
OUT
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0832BV
CY7C0833AV 270 400 200 310 mA
Standby Current (Both Ports TTL Level)
CEL and CER ≥ VIH, f = f
MAX
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = f
MAX
Standby Current (Both Ports CMOS Level)
and CER ≥ V
CE
L
Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = f
Operating Current (VDD = Max, I
= 0 mA, f = 0) Outputs Disabled
– 0.2V, f = 0
DD
MAX
CY7C0833AV 70 100 70 100 mA
OUT
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage...........................................> 2000V
(JEDEC JESD22-A114-2000B)
Latch Up Current....................................................> 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V±165 mV
Industrial –40°C to +85°C 3.3V±165 mV
-167 -133 -100
Min Typ Max Min Typ Max Min Typ Max
225 300 225 300 mA
90 115 90 115 90 115 mA
160 210 160 210 160 210 mA
55 75 55 75 55 75 mA
160 210 160 210 160 210 mA
Ambient
T emperature
V
DD
Unit
Capacitance
Part Number
CY7C0837AV/CY7C0830AV/CY7C0831AV C
CY7C0832AV/CY7C0832BV
CY7C0833AV C
Document #: 38-06059 Rev. *S Page 12 of 28
[26]
Parameter Description Test Conditions Max Unit
IN
C
OUT
IN
C
OUT
Input Capacitance TA = 25°C,
f = 1 MHz,
Output Capacitance 10 pF
VDD = 3.3V
Input Capacitance 22 pF
Output Capacitance 20 pF
13 pF
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Characteristics
R1 = 590
Ω
R2 = 435
Ω
C = 5 pF
(b) Three-state Delay (Load 2)
90%
10%
3.0V
Vss
90%
10%
<
2ns < 2ns
ALL INPUT PULSES
3.3V
VTH = 1.5V
R = 50
Ω
Z0 = 50
Ω
(a) Normal Load (Load 1)
C = 10 pF
OUTPUT
OUTPUT
Note
27.Except JTAG signals (t
r
and tf < 10 ns [max.]).
Over the Operating Range
Parameter Description
f
MAX2
t
CYC2
t
CH2
t
CL2
[27]
t
R
[27]
t
F
t
SA
t
HA
t
SB
t
HB
t
SC
t
HC
t
SW
t
HW
t
SD
t
HD
t
SAD
t
HAD
t
SCN
t
HCN
t
SRST
t
HRST
t
SCM
Maximum Operating Frequency 167 133 133 100 MHz
Clock Cycle Time 6.0 7.5 7.5 10 ns
Clock HIGH Time 2.7 3.0 3.0 4.0 ns
Clock LOW Time 2.7 3.0 3.0 4.0 ns
Clock Rise Time 2.0 2.0 2.0 3.0 ns
Clock Fall Time 2.0 2.0 2.0 3.0 ns
Address Setup Time 2.3 2.5 2.5 3.0 ns
Address Hold Time 0.6 0.6 0.6 0.6 ns
Byte Select Setup Time 2.3 2.5 2.5 3.0 ns
Byte Select Hold Time 0.6 0.6 0.6 0.6 ns
Chip Enable Setup Time 2.3 2.5 NA NA ns
Chip Enable Hold Time 0.6 0.6 NA NA ns
R/W Setup Time 2.3 2.5 2.5 3.0 ns
R/W Hold Time 0.6 0.6 0.6 0.6 ns
Input Data Setup Time 2.3 2.5 2.5 3.0 ns
Input Data Hold Time 0.6 0.6 0.6 0.6 ns
ADS Setup Time 2.3 2.5 NA NA ns
ADS Hold Time 0.6 0.6 NA NA ns
CNTEN Setup Time 2 .3 2.5 NA NA ns
CNTEN Hold Time 0.6 0.6 NA NA ns
CNTRST Setup Time 2.3 2.5 NA NA ns
CNTRST Hold Time 0.6 0.6 NA NA ns
CNT/MSK Setup Time 2.3 2.5 NA NA ns
Figure 6. AC Test Load and Waveforms
-167 -133 -100
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0832BV
Min Max Min Max Min Max Min Max
CY7C0833AV CY7C0833AV
Unit
Document #: 38-06059 Rev. *S Page 13 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Characteristics
Notes
28.This parameter is guaranteed by design, but is not production tested.
29.Test conditions used are Load 2.
Over the Operating Range
Parameter Description
t
HCM
t
OE
[28,29]
t
OLZ
[28,29]
t
OHZ
t
CD2
t
CA2
t
CM2
t
DC
[28,29]
t
CKHZ
[28, 29]
t
CKLZ
t
SINT
t
RINT
t
SCINT
t
RCINT
Port to Port Delays
t
CCS
Master Reset Timing
t
RS
t
RS
t
RSR
t
RSF
t
RSCNTINT
CNT/MSK Hold Time 0.6 0.6 NA NA ns
Output Enable to Data V a lid 4.0 4.4 4.7 5.0 ns
OE to Low Z 0 0 ns
OE to High Z 0 4.0 0 4.4 4.7 5.0 ns
Clock to Data Valid 4.0 4.4 4.7 5.0 ns
Clock to Counter Address Valid 4.0 4.4 NA NA ns
Clock to Mask Register Readback Valid 4.0 4.4 NA NA ns
Data Output Hold After Clock HIGH 1.0 1.0 1.0 1.0 ns
Clock HIGH to Output High Z 0 4.0 0 4.4 4.7 5.0 ns
Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Clock to Clock Skew 5.2 6.0 6.0 8.0 ns
Master Reset Pulse Width 7.0 7.5 7.5 10 ns
Master Reset Setup Time 6.0 6.0 6.0 8.5 ns
Master Reset Recovery Time 6.0 7.5 7.5 10 ns
Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns
Master Reset to Counter Interrupt Flag
Reset Time
(continued)
-167 -133 -100
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0832BV
CY7C0833AV CY7C0833AV
Min Max Min Max Min Max Min Max
10.0 10.0 NA NA ns
Unit
Document #: 38-06059 Rev. *S Page 14 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
JTAG Timing and Switching Waveforms
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
TDO
t
TCYC
t
TMSH
t
TL
t
TH
t
TMSS
t
TDIS
t
TDIH
t
TDOX
t
TDOV
Parameter Description
f
JTAG
t
TCYC
t
TH
t
TL
t
TMSS
t
TMSH
t
TDIS
t
TDIH
t
TDOV
t
TDOX
Maximum JTAG TAP Controller Frequency 10 MHz
TCK Clock Cycle Time 100 ns
TCK Clock HIGH Time 40 ns
TCK Clock LOW Time 40 ns
TMS Setup to TCK Clock Rise 10 ns
TMS Hold After TCK Clock Rise 10 ns
TDI Setup to TCK Clock Rise 10 ns
TDI Hold After TCK Clock Rise 10 ns
TCK Clock LOW to TDO Valid 30 ns
TCK Clock LOW to TDO Invalid 0 ns
Figure 7. JTAG Switching Waveform
CY7C0837AV/CY7C0830AV
CY7C0831AV/CY7C0832AV
CY7C0832BV/CY7C0833AV
Min Max
Unit
Document #: 38-06059 Rev. *S Page 15 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
MRST
t
RSR
t
RS
INACTIVE
ACTIVE
TMS
TDO
INT
CNTINT
t
RSF
t
RSS
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
t
CH2
t
CL2
t
CYC2
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
A
n
A
n+1
CLK
CE
R/W
ADDRESS
DATA
OUT
OE
A
n+2
A
n+3
t
SC
t
HC
t
OHZ
t
OE
t
OLZ
t
DC
t
CD2
t
CKLZ
Q
n
Q
n+1
Q
n+2
1 Latency
BE0
–BE1
t
SB
t
HB
Notes
30.OE
is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
31.ADS
= CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
32.The output is disabled (high-impedance state) by CE
= VIH following the next rising edge of the clock.
33.Addresses need not be accessed sequentially because ADS
= CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Figure 8. Master Reset
Figure 9. Read Cycle
[12, 30, 31, 32, 33]
Document #: 38-06059 Rev. *S Page 16 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
Q
3
Q
1
Q
0
Q
2
A
0
A
1
A
2
A
3
A
4
A
5
Q
4
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
t
SC
t
HC
t
SA
t
HA
t
SC
t
HC
t
SC
t
HC
t
SC
t
HC
t
CKHZ
t
DC
t
DC
t
CD2
t
CKLZ
t
CD2
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CKHZ
t
CKLZ
t
CD2
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
(B1)
CE
(B1)
DATA
OUT(B2)
DATA
OUT(B1)
ADDRESS
(B2)
CE
(B2)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
t
HW
t
SW
t
CD2
t
CKHZ
tSDt
HD
t
CKLZ
t
CD2
NO OPERATION WRITEREAD READ
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
A
n
A
n+1
A
n+2
A
n+2
D
n+2
A
n+3
A
n+4
Q
n
Q
n+3
Notes
34.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS
(B1)
= ADDRESS
(B2)
.
35. ADS
= CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
36.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
37.During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
38. CE
0
= OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
39.CE
0
= BE0 – BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, because OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
(continued)
Figure 10. Bank Select Read
[34, 35]
Figure 11. Read-to-Write-to-Read (OE = LOW)
Document #: 38-06059 Rev. *S Page 17 of 28
[33, 36, 37, 38, 39]
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
A
n
A
n+1
A
n+2
A
n+3
A
n+4
A
n+5
t
HW
t
SW
tSDt
HD
D
n+2
t
CD2
t
OHZ
READ READWRITE
D
n+3
Q
n
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
OE
Q
n+4
t
CD2
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
A
n
COUNTER HOLD
READ WITH COUNTER
t
SAD
t
HAD
t
SCN
t
HCN
t
SAD
t
HAD
t
SCN
t
HCN
Q
x–1
Q
x
Q
n
Q
n+1
Q
n+2
Q
n+3
t
DC
t
CD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
ADS
CNTEN
DATA
OUT
(continued)
Figure 12. Read-to-Write-to-Read (OE
Controlled)
[33, 36, 38, 39]
Figure 13. Read with Address Counter Advance
Document #: 38-06059 Rev. *S Page 18 of 28
[38]
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
t
CH2
t
CL2
t
CYC2
A
n
A
n+1
A
n+2
A
n+3
A
n+4
D
n+1
D
n+1
D
n+2
D
n+3
D
n+4
A
n
D
n
t
SAD
t
HAD
t
SCN
t
HCN
t
SD
t
HD
WRITE EXTERNAL
WRITE WITH COUNTER
ADDRESS
WRITE WITH
COUNTER
WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
DATA
IN
ADDRESS
t
SA
t
HA
CNTEN
ADS
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATA
IN
ADDRESS
CNTRST
R/W
DATA
OUT
A
n
A
m
A
p
A
x
0
1
A
n
A
m
A
p
Q
1
Q
n
Q
0
D
0
t
CH2tCL2
t
CYC2
t
SA
t
HA
t
SW
t
HW
t
SRST
t
HRST
t
SD
t
HD
t
CD2
t
CD2
t
CKLZ
[42]
RESET ADDRESS 0
COUNTER WRITE READ
ADDRESS 0 ADDRESS 1
READ READ
ADDRESS A
n
ADDRESS A
m
READ
Notes
40.CE
0
= BE0 – BE1 = LOW; CE1 = MRST = CNT/MSK = HIGH.
41.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
42.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
(continued)
Figure 14. Write with Address Counter Advance
[39]
Figure 15. Counter Reset
Document #: 38-06059 Rev. *S Page 19 of 28
[40, 41]
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
CNTEN
CLK
t
CH2tCL2
t
CYC2
ADDRESS
ADS
A
n
Q
x-2
Q
x-1
Q
n
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
LOAD
ADDRESS
EXTERNAL
t
CD2
INTERNAL
ADDRESS
A
n+1
A
n+2
A
n
t
CKHZ
DATA
OUT
A
n*
Q
n+3
Q
n+1
Q
n+2
A
n+3
A
n+4
t
CKLZ
t
CA2
or t
CM2
READBACK
INTERNAL
COUNTER
ADDRESS
INCREMENT
EXTERNAL
A
0–A16
Notes
43.CE
0
= OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
44.Address in output mode. Host must not be driving address bus after t
CKLZ
in next clock cycle.
45.Address in input mode. Host can drive address bus after t
CKHZ
.
46.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK
level) being Read out on the address lines.
Figure 16. Readback State of Address Counter or Mask Register
(continued)
[43, 44, 45, 46]
Document #: 38-06059 Rev. *S Page 20 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
t
SA
t
HA
t
SW
t
HW
t
CH2
t
CL2
t
CYC2
CLK
L
R/W
L
A
n
D
n
t
CKHZ
t
HD
t
SA
A
n
t
HA
Q
n
t
DC
t
CCS
t
SD
t
CKLZ
t
CH2
t
CL2
t
CYC2
t
CD2
L_PORT
ADDRESS
L_PORT
DATA
IN
CLK
R
R/W
R
R_PORT
ADDRESS
R_PORT
DATA
OUT
Notes
47.CE
0
= OE = ADS = CNTEN = BE0 – BE1 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
48.This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
CCS
is violated, indeterminate data is Read out.
49.If t
CCS
< minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * t
CYC2
+ t
CD2
) after the rising edge of R_Port's clock. If t
CCS
>
minimum specified value, then R_Port is Read the most recent data (written by L_Port) (t
CYC2
+ t
CD2
) after the rising edge of R_Port's clock.
Figure 17. Left_Port (L_Port) Write to Right_Port (R_Port) Read
(continued)
[47, 48, 49]
Document #: 38-06059 Rev. *S Page 21 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
t
CH2
t
CL2
t
CYC2
CLK
3FFFD 3FFFF
INTERNAL
ADDRESS
Last_Loaded
Last_Loaded +1
t
HCM
COUNTER
3FFFE
CNTINT
t
SCINT
t
RCINT
3FFFC
CNTEN
ADS
CNT/MSK
t
SCM
Notes
50.CE
0
= OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
51.CNTINT
is always driven.
52.CNTINT
goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
53.The mask register assumed to have the value of 3FFFFh.
(continued)
Figure 18. Counter Interrupt and Retransmit
[15, 42, 50, 51, 52, 53]
Document #: 38-06059 Rev. *S Page 22 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Switching Waveforms
t
CH2
t
CL2
t
CYC2
CLK
L
t
CH2
t
CL2
t
CYC2
CLK
R
7FFFF
t
SAtHA
A
n+3
A
n
A
n+1
A
n+2
L_PORT
ADDRESS
A
m
A
m+4
A
m+1
7FFFF
A
m+3
R_PORT
ADDRESS
INT
R
tSAt
HA
t
SINT
t
RINT
Notes
54.CE
0
= OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
55.Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.
56.L_Port is configured for Write operation, and R_Port is configured for Read operation.
57.At least one byte enable (BE0
– BE1) is required to be active during interrupt operations.
58.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
59.OE
is an asynchronous input signal.
60.When CE
changes state, deselection and Read happen after one cycle of latency.
61.CE
0
= OE = LOW; CE1 = R/W = HIGH.
(continued)
Figure 19. MailBox Interrupt Timing
[54, 55, 56, 57, 58]
Table 7. Read/Write and Enable Operation (Any Port)
[2, 17, 59, 60, 61]
Inputs Outputs
OE CLK CE
0
CE
1
R/W DQ0 – DQ
17
X H X X High-Z Deselected
X X L X High-Z Deselected
XLHLD
LLHHD
IN
OUT
Write
Read
H X L H X High-Z Outputs Disabled
Operation
Document #: 38-06059 Rev. *S Page 23 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Ordering Information
512K × 18 (9M) 3.3V Synchronous CY7C0833AV Dual-Port SRAM
Speed
(MHz)
133 CY7C0833AV-133BBC 51-85141
100 CY7C0833AV-100BBC 51-85141
Ordering Code
CY7C0833AV-133BBI 51-85141
CY7C0833AV-100BBI 51-85141
256K × 18 (4M) 3.3V Synchronous CY7C0832AV/CY7C0832BV Dual-Port SRAM
Speed
(MHz)
167 CY7C0832AV-167BBC 51-85141
133 CY7C0832AV-133BBC 51-85141
Ordering Code
CY7C0832AV-167AC 51-85100
CY7C0832AV-167AXC
CY7C0832AV-133AC 51-85100
CY7C0832AV-133AXC
CY7C0832AV-133BBI 51-85141
CY7C0832BV-133AI 51-85100
CY7C0832AV-133AXI
128K × 18 (2M) 3.3V Synchronous CY7C0831AV Dual-Port SRAM
Speed
(MHz)
167 CY7C0831AV-167BBC 51-85141
133 CY7C0831AV-133BBC 51-85141
Ordering Code
CY7C0831AV-167AC 51-85100
CY7C0831AV-167AXC
CY7C0831AV-133BBXC
CY7C0831AV-133AC 51-85100
CY7C0831AV-133AXC
CY7C0831AV-133BBI 51-85141
CY7C0831AV-133BBXI
CY7C0831AV-133AI 51-85100
CY7C0831AV-133AXI
64K × 18 (1M) 3.3V Synchronous CY7C0830AV Dual-Port SRAM
Speed
(MHz)
167 CY7C0830AV-167BBC 51-85141
133 CY7C0830AV-133BBC 51-85141
Ordering Code
CY7C0830AV-167AC 51-85100
CY7C0830AV-133AC 51-85100
CY7C0830AV-133BBI 51-85141
CY7C0830AV-133AI 51-85100
Package
Diagram
Package
Diagram
Package
Diagram
Package
Diagram
Package Type
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
Package Type
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
Package Type
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch (Pb-Free)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch (Pb-Free)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm) (Pb-Free)
Package Type
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch
120-Pin Thin Quad Flat Pack (14 x 14 x 1.4 mm)
Operating
Range
Commercial
Industrial
Commercial
Industrial
Operating
Range
Commercial
Commercial
Industrial
Operating
Range
Commercial
Commercial
Industrial
Operating
Range
Commercial
Commercial
Industrial
Document #: 38-06059 Rev. *S Page 24 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Ordering Information
SEATING PLANE
Ø0.50 (144X)
0.40±0.05
1.60MAX.
0.70±0.05
A1 CORNER
11.00
1.00
13.00±0.10
13.00±0.10
1.00
11.00
F
M
J
K
L
H
G
C
D
E
B
A
12
911
10
7
6
8
35
4
1
2
Ø0.05 M C
Ø0.25MCAB
C
M
L
K
F
H
J
G
E
D
A
B
1
12
11
2
10
39
4
8
567
5.50
5.50
13.00±0.10
13.00±0.10
0.36
+0.10
-0.05
0.25 C
0.15 C
//
A
B
0.15(4X)
C
A
B
TOP VIEW
BOTTOM VIEW
DIMENSIONS IN MILLIMETERS
REFERENCE JEDEC: PUBLICATION 95
PKG. WEIGHT: 0.53 gms
DESIGN GUIDE 4.14D
51-85141-*B
32K × 18 (512K) 3.3V Synchronous CY7C0837AV Dual-Port SRAM
Speed
(MHz)
Ordering Code
167 CY7C0837AV-167BBC 5 1-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Commercial
133 CY7C0837AV-133BBC 5 1-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Commercial
CY7C0837AV-133BBI 51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Industrial
Package
Diagram
Package Type
Operating
Range
Package Diagrams
Figure 20. 144-Ball FBGA (13 x 13 x 1.6 m m) (51-85141)
Document #: 38-06059 Rev. *S Page 25 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Package Diagrams
51-85100-**
Figure 21. 120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) (51-85100)
Document #: 38-06059 Rev. *S Page 26 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document History Page
Document Title: CY7C0837AV/CY7C0830AV/CY7C0831AV/CY7C0832AV/CY7C0832BV/CY7C0833AV, FLEx18™ 3.3V
64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
Document Number: 38-06059
Rev. ECN No.
Orig. of
Change
** 111473 DSG 11/27/01 Change from Spec number: 38-01056 to 38-06059
*A 111942 JFU 12/21/01 Up dated capacitance values
*B 113741 KRE 04/02/02 Updated I
*C 114704 KRE 04/24/02 Added discussion of Pause/Restart for JTAG boundary scan
*D 115336 KRE 07/01/02 Revised speed offerings for all densities
*E 122307 RBI 12/27/02 Power up requirements added to Maximum Ratings Information
*F 1 23636 KRE 1/27/03 Revise t
*G 126053 SPN 08/11/03 Separated out 4M and 9M data sheets
*H 129443 RAZ 11/03/03 Updated I
*I 231993 YDT See ECN Removed “A particular port can write to a certain location while another port is
*J 231813 WWZ See ECN Removed x36 devices (CY7C0852/CY7C0851) from this datasheet. Added
*K 311054 RYQ See ECN Minor Change: Corre c t the revision indicated on the footer.
*L 329111 SPN See ECN Updated Marketing part numbers
*M 330561 RUY See ECN Added Byte Select Operation T able
*N 375198 YDT See ECN Removed Preliminary status
*O 391525 SPN See ECN Updated Counter reset section to reflect what is loaded into the mirror register
*P 414109 LIJ See ECN Corrected Ordering Codes for 0831 devices in the 133 Mhz speed bin.
*Q 461113 YDT SEE ECN Changed VDDIO to VDD (typo)
*R 2544945 VKN/AESA 07/29/08 Updated Template. Updated ordering information
*S 2668478 VKN/PYRS 02/04/09 Added CY7C0832BV part
Submission
Date
Description of Change
Updated switching parameters and I
SB3
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding I
sb
values
SB3
Updated ESD voltage
Corrected 0853 pins L3 and L12
cd2
, tOE, t
OHZ
, t
CKHZ
, t
CKLZ
for the CY7C0853V to 4.7 ns
Updated I
sb
sb
and I
and I
CC
CC
values
values
reading that location.” from Func ti on a l Description.
0.5M, 1M and 9M x18 devices to it. Changed title to FLEx18 3.3V
32K/64K/128K/256K/512K x18 Synchronous Dual-Port RAM. Changed
datasheet to accommodate the removals and additions. Removed general
JTAG description. Updated JTAG ID codes for all devices. Added 144FBGA
package for all devices. Updated selection guide table and moved to the front
page. Updated block diagram to reflect x18 configuration. Added preliminary
status back due to the addition of the new devices.
Updated tRSF
Added I
Changed t
SB5
RSCNTINT
to 10ns
Added CY7C0833AV-133BBI.
Added lead(Pb)-free parts
Corrected typo in DC table
Added footnote #1
Updated Ordering information table
Document #: 38-06059 Rev. *S Page 27 of 28
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corpo rati on assu mes no respo nsibili ty fo r the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life sa ving, critical control or safety applications, un l ess p ur suant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its pro ducts for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/ or firm ware) i s own ed by Cypre ss Se micond ucto r Corp oratio n (Cy press ) and is pr otec ted by and s ubj ect to worldwide patent protection (United States and foreign),
United States co pyri ght la ws and inte rnati ona l t reaty p rovis ions. Cyp ress he reby gr ant s to licensee a per sonal , non- exclu siv e, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpos e of creating custom sof tware and or firm ware in support of li censee product to be use d only in conjuncti on with a Cypress
integrated circuit as specified i n the applicable agreement. Any reproductio n, modification, translation , compilation, o r represent ation of this So urce Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the ap plic ation or use o f an y product o r c ircuit describe d her ein. Cypress d oes not aut hori ze it s product s fo r use as critical component s in life-sup port systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06059 Rev. *S Revised March 03, 2009 Page 28 of 28
FLEx18 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
Loading...