Cypress CY7C0430BV, CY7C0430CV User Manual
CY7C0430BV
CY7C0430CV
10 Gb/s 3.3V QuadPort™ DSE Family
Features
• QuadPort™ datapath switching element (DSE) family
allows four independent ports of access for data path
management and switching
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz
• High-speed clock to data access 4.2 ns (max.)
• Synchronous pipelined device
— 1-Mb (64K × 18) switch array
• 0.25-micron CMOS for optimum speed/power
• IEEE 1149.1 JTAG boundary scan
• Width and depth expansion capabilities
• BIST (Built-In Self-Test) controller
[1]
port speed x 18-bit-wide interface × 4 ports
QuadPort DSE Family Applications
PORT 1
• Dual Chip Enables on all ports for easy depth expansion
• Separate upper-byte and lower-byte controls on all
ports
• Simple array partitioning
— Internal mask register controls counter wrap-around
— Counter-Interrupt flags to indicate wrap-around
— Counter and mask registers readback on address
• 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball
pitch)
• Commercial and industrial temperature ranges
• 3.3V low operating power
— Active = 750 mA (maximum)
— Standby = 15 mA (maximum
PORT 3
PORT 2
PORT 1 PORT 3
Note:
for commercial is 135 MHz and for industrial is 133 MHz.
1. f
MAX2
PORT 4
BUFFERED SWITCH
PORT 2
PORT 4
REDUNDANT DATA MIRROR
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06027 Rev. *B Revised May 23, 2006
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CY7C0430BV
CY7C0430CV
PORT 1
PORT 2
PORT 3
DATA PATH AGGREGATOR
Processor 1
Pre-processed DATA Path Processed DATA Path
PARALLEL PACKET PROCESSING
QuadPort
DSE Family
Processor 2
DATA PATH MANAGER FOR
PORT 4
PORT 1 PORT 3
PORT 2 PORT 4
DATA CLASSIFICATION ENGINE
Functional Description
The Quadport Datapath Switching Element (DSE) family offers
four ports that may be clocked at independent frequencies
from one another. Each port can read or write up to 133 MHz
giving the device up to 10 Gb/s of data throughput. The device
is 1-Mb (64K × 18) in density. Simultaneous reads are allowed
for accesses to the same address location; however, simultaneous reading and writing to the same address is not allowed.
Any port can write to a certain location while other ports are
reading that location simultaneously, if the timing spec for port
to port delay (t
location by more than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
t
= 4.2 ns. Each port contains a burst counter on the input
CD2
) is met. The result of writing to the same
CCS
[1]
Queue #1
Queue #2
address register. After externally loading the counter with the
initial address the counter will self-increment the address internally (more details to follow). The internal write pulse width is
independent of the duration of the R/W
internal write pulse is self-timed to allow the shortest possible
,
cycle times.
A HIGH on CE
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430BV and CY7C0430CV (64K × 18 device)
supports burst contains for simple array partitioning. Counter
enable inputs are provided to stall the operation of the address
input and utilize the internal address generated by the internal
counter for fast interleaved memory applications. A port’s burst
or LOW on CE1 for one clock cycle will power
0
input signal. The
Document #: 38-06027 Rev. *B Page 2 of 37
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CY7C0430BV
CY7C0430CV
counter is loaded with an external address when the port’s
Counter Load pin (CNTLD
Counter Increment pin (CNTINC
) is asserted LOW. When the port’s
) is asserted, the address
counter will increment on each subsequent LOW-to- HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until
CNTINC
is deasserted. The counter can address the entire
switch array and will loop back to the start. Counter Reset
(CNTRST) is used to reset the burst counter. A counter-mask
register is used to control the counter wrap. The counter and
Top Level Logic Block Diagram
Port 1 Operation-control Logic Blocks
UB
P1
LB
P1
R/W
P1
OE
P1
CE
0P1
CE
1P1
CLK
P1
18
I/O
- I/O
0P1
17P1
CLK
P1
A
0P1–A15P1
MKLD
CNTLD
CNTINC
CNTRD
MKRD
CNTRST
CNTINT
P1
INT
16
P1
P1
P1
P1
P1
P1
P1
[2]
Port-1
Control
Logic
Port 1
I/O
Port 1
Counter/
Mask Reg/
Address
Decode
mask register operations are described in more details in the
following sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating MKRD
or CNTRD,
respectively.
The new features included for the QuadPort DSE family
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, readback of mask register value on address
lines, interrupt flags for message passing, BIST, JTAG for
boundary scan, and asynchronous Master Reset.
MRST
TMS
TCK
TDI
CLKBIST
Port 1
Reset
Logic
JTAG
Controller
BIST
Port 4 Logic Blocks
Port 4
TDO
[3]
64K × 18
QuadPort DSE
Array
Port 2
Port 3
Port 2 Logic Blocks
Notes:
2. Port 1 Control Logic Block is detailed on page 4.
3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
[3]
Port 3 Logic Blocks
[3]
Document #: 38-06027 Rev. *B Page 3 of 37
[+] Feedback
Port 1 Operation-Control Logic Block Diagram
(Address Readback is independent of CEs)
R/W
CE
CE
LB
OE
UB
0P1
1P1
P1
P1
P1
P1
W
CY7C0430BV
CY7C0430CV
A
0P1–A15P1
CNTRD
MKRD
MKLD
CNTINC
CNTLD
CNTRST
CLK
CNTINT
MRST
P1
P1
P1
P1
P1
P1
P1
MRST
P1
I/O
16
Priority
Decision
Logic
I/O
9P1
0P1
–I/O
–I/O
17P1
8P1
9
9
Addr.
Read
Port 1
Readback
Register
Port 1
Mask Register
Port 1
Counter/
Address
Register
LB
UB
R/W
CE
0P1
CE
1P1
OE
P1
CLK
MRST
P1
P1
P1
P1
Port-1
I/O
Control
Port 1
Address
Decode
Port 1
Interrupt
Logic
P
Po
or
r
t 2
INT
1
t
64K × 18
QuadPort
DSE Array
P1
P
ort 4
ort 3
P
Document #: 38-06027 Rev. *B Page 4 of 37
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CY7C0430BV
CY7C0430CV
Pin Configuration
272-ball Grid Array (BGA)
Top Vi e w
1234567891011121314151617181920
LBP1I/O17P2I/O15P2I/O13P2I/O11P2I/O9P2I/O16P1I/O14P1I/O12P1I/O10P1I/O10P4I/O12P4I/O14P4I/O16P4I/O9P3I/O11P3I/O13P3I/O15P3I/O17P3 LB
A
VDD1 UBP1I/O16P2I/O14P2I/O12P2I/O10P2I/O17P1I/O13P1I/O11P1TMS TDI I/O11P4I/O13P4I/O17P4I/O10P3I/O12P3I/O14P3I/O16P3UBP4VDD1
B
A14P1A15P1CE1P1CE0P1R/WP1I/O15P1VSS2 VSS2 I/O9P1 TCK TDO I/O9P4VSS2 VSS2 I/O15P4R/WP4CE0P4CE1P4A15P4A14
C
P4
P4
VSS1 A12P1A13P1 OE
D
A10P1A11P1MKRD
E
A7P1A8P1A9P1CNTINT
F
VSS1 A5P1A6P1CNTINC
G
A3P1A4P1MKLDP1CNTLD
H
VDD1 A1P1A2P1VDD GND
J
A0P1INTP1 CNTRSTP1CLK
K
A0P2INTP2CNTRSTP2 VSS GND
L
VDD1 A1P2A2P2CLK
M
A3P2A4P2MKLDP2CNTLD
N
VSS1 A5P2A6P2CNTINC
P
A7P2A8P2A9P2CNTINT
R
A10P2A11P2MKRD
T
P1
P2
VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OEP4A13P4A12P4VSS1
P1
CNTRD
P1
P1
P1
P1
P1
P2
P2
P2
P2
CNTRD
P2
GND
GND
MKRDP4A11P4A10
CNTRD
P4
CNTINT
P4A9P4A8P4
CNTINCP4A6P4A5P4 VSS1
CNTLDP4MKLDP4A4P4A3
[4]
[4]
[4]
GND
GND
[4]
[4]
GND
GND
[4]
[4]
GND
GND
[4]
[4]
GND
GND
[4]
GND
[4]
[4]
GND
[4]
[4]
GND
[4]
[4]
GND
VDD A2P4A1P4VDD1
CLKP4CNTRSTP4INTP4 A0
VSS CNTRSTP3INTP3 A0
CLKP3A2P3A1P3VDD1
CNTLDP3MKLDP3A4P3A3
CNTINC
P3A6P3A5P3
CNTINTP3A9P3A8P3 A7
MKRDP3A11P3A10
CNTRD
P3
P4
A7
P4
P4
P4
P3
P3
VSS1
P3
P3
VSS1 A12P2A13P2 OE
U
A14P2A15P2CE1P2 CE0
V
VDD1 UB
W
Y
P2
I/O8P1I/O6P1I/O4P1I/O2P1I/O0P11/O7P2I/O5P2I/O3P2I/O1P2I/O1P3I/O3P3I/O5P3I/O7P3I/O0P4I/O2P4I/O4P4I/O6P4I/O8P4LB
LB
P2
I/O7P1I/O5P1I/O3P1I/O1P1I/O8P2I/O4P2I/O2P2MRST
VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OEP3A13P3A12P3VSS1
P2
R/WP2I/O6P2VSS2 VSS2 I/O0P2NC NC I/O0P3VSS2 VSS2 I/O6P3R/WP3CE0P3CE1P3A15P3A14
P2
CLKBIST I/O2P3I/O4P3I/O8P3I/O1P4I/O3P4I/O5P4I/O7P4UB
P3
VDD1
P3
P3
Note:
4. Central Leads are for thermal dissipation only. They are connected to device V
.
SS
Document #: 38-06027 Rev. *B Page 5 of 37
[+] Feedback
CY7C0430BV
CY7C0430CV
Selection Guide
CY7C0430CV
–133
f
MAX2
133
[1]
Max Access Time (Clock to Data) 4.2 5.0 ns
Max Operating Current I
Max Standby Current for I
Max Standby Current for I
CC
(All ports TTL Level) 200 150 mA
SB1
(All ports CMOS Level) 15 15 mA
SB3
750 600 mA
Pin Definitions
Port 1 Port 2 Port 3 Port 4 Description
A
0P1–A15P1
I/O
–I/O
0P1
CLK
P1
LB
P1
UB
P1
CE
,CE
0P1
OE
P1
R/W
P1
MRST Master Reset Input. This is one signal for All Ports.
CNTRST
MKLD
CNTLD
CNTINC
P1
P1
P1
P1
17P1
1P1
A
0P2–A15P2
I/O
–I/O
0P2
CLK
P2
LB
P2
UB
P2
CE
,CE
0P2
OE
P2
R/W
P2
CNTRST
MKLD
P2
CNTLD
CNTINC
P2
P2
1P2
P2
17P2
A
0P3–A15P3
I/O
–I/O
0P3
CLK
P3
LB
P3
UB
P3
CE
,CE
0P3
OE
P3
R/W
P3
CNTRST
MKLD
P3
CNTLD
CNTINC
P3
P3
1P3
P3
17P3
A
0P4–A15P4
I/O
–I/O
0P4
CLK
P4
LB
P4
UB
P4
CE
,CE
0P4
OE
P4
R/W
P4
CNTRST
MKLD
P4
CNTLD
CNTINC
P4
P4
P4
Address Input/Output.
Data Bus Input/Output.
17P4
Clock Input. This input can be free running or strobed.
Maximum clock input rate is f
Lower Byte Select Input. Asserting this signal LOW
enables read and write operations to the lower byte. For
read operations both the LB and OE signals must be
asserted to drive output data on the lower byte of the data
pins.
Upper Byte Select Input. Same function as LB, but to the
upper byte.
Chip Enable Input. To select any port, both CE0 AND
1P4
CE
must be asserted to their active states (CE0 ≤ VIL and
1
CE
≥ VIH).
1
Output Enable Input. This signal must be asserted LOW
to enable the I/O data lines during read operations. OE
asynchronous input.
Read/Write Enable Input. This signal is asserted LOW
to write to the dual port memory array. For read operations, assert this pin HIGH.
MRST
is an asynchronous input. Asserting MRST LOW
performs all of the reset functions as described in the text.
A MRST
operation is required at power-up.
Counter Reset Input. Asserting this signal LOW resets
the burst address counter of its respective port to zero.
CNTRST
is second to MRST in priority with respect to
counter and mask register operations.
Mask Register Load Input. Asserting this signal LOW
loads the mask register with the external address
available on the address lines. MKLD
higher priority over CNTLD
Counter Load Input. Asserting this signal LOW loads the
burst counter with the external address present on the
address pins.
Counter Increment Input. Asserting this signal LOW
increments the burst address counter of its respective port
on each rising edge of CLK.
CY7C0430CV
–100 Unit
100 MHz
.
MAX
operation has
operation.
is
Document #: 38-06027 Rev. *B Page 6 of 37
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CY7C0430BV
CY7C0430CV
Pin Definitions (continued)
Port 1 Port 2 Port 3 Port 4 Description
CNTRD
MKRD
CNTINT
P1
P1
P1
INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output. Interrupt permits communications
TMS JTAG Test Mode Select Input. It controls the advance of
TCK JTAG Test Clock Input. This can be CLK of any port or
TDI JTAG Test Data Input. This is the only data input. TDI
TDO JTAG Test Data Output. This is the only data output.
CLKBIST BIST Clock Input.
GND Thermal Ground for Heat Dissipation.
V
SS
V
DD
V
SS1
V
DD1
V
SS2
V
DD2
CNTRD
MKRD
CNTINT
P2
P2
P2
CNTRD
MKRD
CNTINT
P3
P3
P3
CNTRD
MKRD
CNTINT
P4
P4
P4
Counter Readback Input. When asserted LOW, the
internal address value of the counter will be read back on
the address lines. During CNTRD
and CNTINC
must be HIGH. Counter readback operation
operation, both CNTLD
has higher priority over mask register readback operation.
Counter readback operation is independent of port chip
enables. If address readback operation occurs with chip
enables active (CE0 = LOW, CE1 = HIGH), the data lines
(I/Os) will be three-stated. The readback timing will be
valid after one no-operation cycle plus t
edge of the next cycle.
from the rising
CD2
Mask Register Readback Input. When asserted LOW,
the value of the mask register will be readback on address
lines. During mask register readback operation, all
counter and MKLD
inputs must be HIGH (see Counter
and Mask Register Operations truth table). Mask register
readback operation is independent of port chip enables.
If address readback operation occurs with chip enables
active (CE
be three-stated. The readback will be valid after one
no-operation cycle plus t
next cycle.
= LOW, CE1 = HIGH), the data lines (I/Os) will
0
from the rising edge of the
CD2
Counter Interrupt Flag Output. Flag is asserted LOW
for one clock cycle when the counter wraps around to
location zero.
between all four ports. The upper four memory locations
can be used for message passing. Example of operation:
INT
is asserted LOW when another port writes to the
P4
mailbox location of Port 4. Flag is cleared when Port 4
reads the contents of its mailbox. The same operation is
applicable to ports 1, 2, and 3.
JTAG TAP state machine. State machine transitions occur
on the rising edge of TCK.
an external clock connected to the JTAG TAP.
inputs will shift data serially in to the selected register.
TDO transitions occur on the falling edge of TCK. TDO
normally three-stated except when captured data is
shifted out of the JTAG TAP.
Ground Input.
Power Input.
Address Lines Ground Input.
Address Lines Power Input.
Data Lines Ground Input.
Data Lines Power Input.
Document #: 38-06027 Rev. *B Page 7 of 37
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Maximum Ratings
CY7C0430BV
CY7C0430CV
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................ –65
°C to + 150°C
Ambient Temperature with
Power Applied............................................–55
°C to + 125°C
Supply Voltage to Ground Potential.............. –0.5V to + 4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to V
DC Input Voltage....................................–0.5V to V
CC
CC
+ 0.5V
+ 0.5V
Electrical Characteristics Over the Operating Range
Parameter Description
V
V
V
V
I
I
I
I
I
I
OH
OL
IH
IL
OZ
CC
SB1
SB2
SB3
SB4
Output HIGH Voltage
(V
= Min., I
CC
= –4.0 mA)
OH
Output LOW Voltage
(V
= Min., I
CC
= +4.0 mA)
OH
Input HIGH Voltage 2.0 2.0 V
Input LOW Voltage 0.8 0.8 V
Output Leakage Current –10 10 –10 10 µA
Operating Current (V
Outputs Disabled, CE
= Max., I
CC
= VIL, f = f
OUT
max
= 0 mA)
Standby Current (four ports toggling at TTL
Levels,0 active)
CE
≥ VIH, f = f
1-4
Standby Current (four ports toggling at TTL
Levels, 1 active)
f = f
MAX
Standby Current (four ports CMOS Level, 0
active)
CE
MAX
CE1 | CE2 | CE3 | CE4 < VIL,
≥ VIH, f = 0
1–4
Standby Current (four ports CMOS Level, 1
active and toggling) CE
, f = f
V
IL
MAX
| CE2 | CE3 | CE4 <
1
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2200V
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 3.3V ± 150 mV
Industrial –40
°C to +85°C 3.3V ± 150 mV
Quadport DSE Family
–133 –100
Min. Typ. Max. Min. Typ. Max.
2.4 2.4 V
0.4 0.4 V
350 700 300 550 mA
80 200 60 150 mA
150 300 125 250 mA
1.5 15 1.5 15 mA
110 290 85 240 mA
DD
Unit
JTAG TAP Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
I
OH1
OL1
IH
IL
X
Output HIGH Voltage I
= −4.0 mA 2.4 V
OH
Output LOW Voltage IOL = 4.0 mA 0.4 V
Input HIGH Voltage 2.0 V
Input LOW Voltage 0.8 V
Input Leakage Current GND ≤ VI ≤ V
DD
–100 100 µA
Capacitance
Parameter Description Test Conditions Max. Unit
CIN (All Pins) Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.3V
C
(All Pins) Output Capacitance 10 pF
OUT
CC
CIN (CLK Pins) Input Capacitance 15 pF
C
(CLK Pins) Output Capacitance 15 pF
OUT
Document #: 38-06027 Rev. *B Page 8 of 37
10 pF
[+] Feedback
AC Test Load
CY7C0430BV
CY7C0430CV
OUTPUT
Z0 = 50Ω
C
(a) Normal Load
TDO
Z
Note:
5. Test conditions: C = 10 pF.
R = 50Ω
[5]
=50Ω
0
(c) TAP Load
VTH=1.5V
1.5V
50Ω
C
GND
= 10 pF
OUTPUT
OUTPUT
3.0V
GND
Z0 = 50Ω
5 pF
Z0 = 50Ω
5 pF
(b) Three-State Delay
10%
t
R
90%
All Input Pulses
R = 50Ω
R = 50Ω
VTH=1.5V
VTH=3.3V
90%
10%
t
F
Document #: 38-06027 Rev. *B Page 9 of 37
[+] Feedback
CY7C0430BV
CY7C0430CV
Switching Characteristics Over the Industrial Operating Range
Parameter Description
[7]
f
MAX2
[7]
t
CYC2
t
CH2
t
CL2
t
R
t
F
t
SA
t
HA
t
SC
t
HC
t
SW
t
HW
t
SD
t
HD
t
SB
t
HB
t
SCLD
t
HCLD
t
SCINC
t
HCINC
t
SCRST
t
HCRST
t
SCRD
t
HCRD
t
SMLD
t
HMLD
t
SMRD
t
HMRD
t
OE
[8]
t
OLZ
[8]
t
OHZ
t
CD2
t
CA2
t
CM2
t
DC
[9]
t
CKHZ
Notes:
6. If data is simultaneously written and read to the same address location and t
remaining in the address is undefined.
7. f
MAX2
8. This parameter is guaranteed by design, but it is not production tested.
9. Valid for both address and data outputs.
Maximum Frequency 133 100 MHz
Clock Cycle Time 7.5 10 ns
Clock HIGH Time 3 4 ns
Clock LOW Time 3 4 ns
Clock Rise Time 2 3 ns
Clock Fall Time 2 3 ns
Address Set-up Time 2.3 3 ns
Address Hold Time 0.7 0.7 ns
Chip Enable Set-up Time 2.3 3 ns
Chip Enable Hold Time 0.7 0.7 ns
R/W Set-up Time 2.3 3 ns
R/W Hold Time 0.7 0.7 ns
Input Data Set-up Time 2.3 3 ns
Input Data Hold Time 0.7 0.7 ns
Byte Set-up Time 2.3 3 ns
Byte Hold Time 0.7 0.7 ns
CNTLD Set-up Time 2.3 3 ns
CNTLD Hold Time 0.7 0.7 ns
CNTINC Set-up Time 2.3 3 ns
CNTINC Hold Time 0.7 0.7 ns
CNTRST Set-up Time 2.3 3 ns
CNTRST Hold Time 0.7 0.7 ns
CNTRD Set-up Time 2.3 3 ns
CNTRD Hold Time 0.7 0.7 ns
MKLD Set-up Time 2.3 3 ns
MKLD Hold Time 0.7 0.7 ns
MKRD Set-up Time 2.3 3 ns
MKRD Hold Time 0.7 0.7 ns
Output Enable to Data Valid 6.5 8 ns
OE to Low-Z 1 1 ns
OE to High-Z 1 6 1 7 ns
Clock to Data Valid 4.2 5 ns
Clock to Counter Address Readback Valid 4.7 5 ns
Clock to Mask Register Readback Valid 4.7 5 ns
Data Output Hold After Clock HIGH 1 1 ns
Clock HIGH to Output High-Z 1 4.8 1 6.8 ns
is violated, the data read from the address, as well as the subsequent data
CCS
for commercial is 135 MHz. t
Min. for commercial is 7.4 ns.
CYC2
[6]
CY7C0430BV and CY7C0430CV
–133 –100
Min. Max. Min. Max.
Unit
Document #: 38-06027 Rev. *B Page 10 of 37
[+] Feedback
CY7C0430BV
CY7C0430CV
Switching Characteristics Over the Industrial Operating Range (continued)
CY7C0430BV and CY7C0430CV
–133 –100
Parameter Description
[9]
t
CKLZ
t
SINT
t
RINT
t
SCINT
t
RCINT
Clock HIGH to Output Low-Z 1 1 ns
Clock to INT Set Time 1 7.5 1 10 ns
Clock to INT Reset Time 1 7.5 1 10 ns
Clock to CNTINT Set Time 1 7.5 1 10 ns
Clock to CNTINT Reset Time 1 7.5 1 10 ns
Min. Max. Min. Max.
Master Reset Timing
t
RS
t
RSR
t
ROF
Master Reset Pulse Width 7.5 10 ns
Master Reset Recovery Time 7.5 10 ns
Master Reset to Output Flags Reset Time 6.5 8 ns
Port to Port Delays
[6]
t
CCS
Clock to Clock Set-up Time (time required after a write
before you can read the same address location)
6.5 9 ns
JTAG Timing and Switching Waveforms
Parameter Description
f
JTAG
t
TCYC
t
TH
t
TL
t
TMSS
t
TMSH
t
TDIS
t
TDIH
t
TDOV
t
TDOX
f
BIST
t
BH
t
BL
Maximum JTAG TAP Controller Frequency 10 MHz
TCK Clock Cycle Time 100 ns
TCK Clock High Time 40 ns
TCK Clock Low Time 40 ns
TMS Set-up to TCK Clock Rise 20 ns
TMS Hold After TCK Clock Rise 20 ns
TDI Set-up to TCK Clock Rise 20 ns
TDI Hold after TCK Clock Rise 20 ns
TCK Clock Low to TDO Valid 20 ns
TCK Clock Low to TDO Invalid 0 ns
Maximum CLKBIST Frequency 50 MHz
CLKBIST High Time 6 ns
CLKBIST Low Time 6 ns
Min. Max.
[6]
Unit
Quadport DSE Family
–133/–100
Unit
Document #: 38-06027 Rev. *B Page 11 of 37
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t
CY7C0430BV
CY7C0430CV
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
Test Data-Out
TDO
Switching Waveforms
Master Reset
CLK
[10]
t
CH2
t
CYC2
t
TMSS
t
CL2
t
TDIS
TH
t
TDOX
t
TDOV
t
TL
t
TMSH
t
TDIH
t
TCYC
t
MRST
t
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
[11]
TMS
CNTINT
INT
TDO
Notes:
is the set-up time required for all input control signals.
10. t
S
11.To Reset the test port without resetting the device, TMS must be held low for five clock cycles.
RSF
RS
t
RSR
INACTIVE
t
S
ACTIVE
Document #: 38-06027 Rev. *B Page 12 of 37
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