Cypress CY7C027V, CY7C037V, CY7C027VN, CY7C027AV, CY7C028V User Manual

CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

3.3V 32K/64K x 16/18 Dual-Port Static
RAM

Features

R/W

L

CE

0L

CE

1L

OE

L

I/O

8/9L

–I/O

15/17L

I/O

Control

Address

Decode

A

0L–A14/15L

CE

L

OE

L

R/W

L

BUSY

L

I/O

Control

CE

L

Interrupt

Semaphore

Arbitration

SEM

L

INT

L

M/S

UB

L

LB

L

I/O0L–I/O

7/8L

R/W

R

CE

0R

CE

1R

OE

R

I/O

8/9L

–I/O

15/17R

CE

R

UB

R

LB

R

I/O0L–I/O

7/8R

UB

L

LB

L

Logic Block Diagram

A0L–A

14/15L

True Dual-Ported

RAM Array

A0R–A

14/15R

CE

R

OE

R

R/W

R

BUSY

R

SEM

R

INT

R

UB

R

LB

R

Address

Decode

A

0R–A14/15R

[3]

[3]

[4]

[4]

[5]

[5]

[6]

[6]

[5] [5]

15/16

8/9

8/9

15/16

8/9

8/9

15/16 15/16

■

True Dual-Ported memory cells which allow
simultaneous access of the same memory location

■

32K x 16 organization (CY7C027V/027VN/027AV

■

64K x 16 organization (CY7C028V)

■

32K x 18 organization (CY7C037V/037AV

■

64K x 18 organization (CY7C038V)

■

0.35 micron CMOS for optimum speed and power

■

High speed access: 15, 20, and 25 ns

■

Low operating power

■

Active: ICC = 115 mA (typical)

■

Standby: I

= 10 μA (typical)

SB3

[2]

)

■

Fully asynchronous operation

■

Automatic power down

■

Expandable data bus to 32/36 bits or more using Master/Slave

[1]

)

chip select when using more than one device

■

On-chip arbitration logic

■

Semaphores included to permit software handshaking
between ports

■

INT flag for port-to-port communication

■

Separate upper-byte and lower-byte control

■

Dual chip enables

■

Pin select for Master or Slave

■

Commercial and Industrial temperature ranges

■

100-pin Pb-free TQFP and 100-pin TQFP

Notes

1. CY7C027V, CY7C027VN and CY7 C027AV are functionally identical.

2. CY7C037V and CY7C037AV are functionally identical.
–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.

3. I/O

8

4. I/O

–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.

0

5. A

0–A14

6. BUSY

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06078 Rev. *B Revised December 09, 2008

for 32K; A0–A15 for 64K devices.

is an output in master mode and an input in slave mode.

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CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Pin Configurations

1

3

2

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

59

60

61

67
66

64

65

63
62

68

69

70

75

73

74

72
71

A9R
A10R
A11R
A12R
A13R
A14R

UBR

NC

LBR

CE1R
SEMR

OER
GND

NC

A15R

GND
R/WR

GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R

CE0R

58
57
56
55
54
53
52
51

CY7C027V/027VN/027AV (32K x 16)

A9L
A10L
A11L
A12L
A13L
A14L

UBL

NC

LBL

CE1L

SEML

OEL

GND

NC

A15L

VCC

R/WL

GND

I/O15L
I/O14L
I/O13L
I/O12L

I/O11L

I/O10L

CE0L

17

16

15

9
10

12

11

13
14

8

7

6

4
5

18
19
20
21
22
23
24
25

A8L

A7L

A6L

A5L

A4L

A3L

INTL

A1L

NC

GND

M/S

A0R

A1R

A0L

A2L

BUSYR

INTR

A2R

A3R

A4R

A5R

A6R

A7R

A8R

BUSYL

34 35 36 424139 403837 43 44 45 5048 494746

NC

I/O9R

I/O8R

I/O7R

VCC

I/O6R

I/01R

I/O4R

I/O2R

GND

I/O0L

I/O2L

I/O3L

I/O3R

I/O5R

I/O1L

GND

I/O4L

I/O5L

I/O6L

I/O7L

VCC

I/O8L

I/O9L

I/O0R

3332313029282726

CY7C028V (64K x 16)

[1]

[1]

Note

1. This pin is NC for CY7C027V/027VN/027AV.

Figure 1. 100-Pin TQFP (Top View)

Document #: 38-06078 Rev. *B Page 2 of 18

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CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Pin Configurations

1

3

2

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

59

60

61

67
66

64

65

63
62

68

69

70

75

73

74

72
71

A8R
A9R
A10R
A11R
A12R
A13R

CE0R

A15R

UBR

SEMR
R/WR

GND
I/O17R

LBR

A14R

GND
OER

GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R

CE1R

58
57
56
55
54
53
52
51

CY7C037V/037AV (32K x 18)

A9L
A10L
A11L
A12L
A13L
A14L

CE1L

LBL

CE0L

R/WL

OEL

I/O17L
I/O16L

UBL

A15L

VCC

GND

GND

I/O15L
I/O14L
I/O13L
I/O12L

I/O11L

I/O10L

SEML

17

16

15

9
10

12

11

13
14

8

7

6

4
5

18
19
20
21
22
23
24
25

A8L

A7L

A6L

A5L

A4L

A3L

BUSYL

A1L

INTL

GND

VCC

INTR

A0R

A0L

A2L

M/S

BUSYR

A1R

A2R

A3R

A4R

A5R

A6R

A7R

GND

34 35 36 424139 403837 43 44 45 5048 494746

I/O10R

I/O9R

I/O8R

I/O7R

VCC

I/O6R

I/01R

I/O4R

I/O2R

GND

I/O0L

I/O2L

I/O3L

I/O3R

I/O5R

I/O1L

GND

I/O4L

I/O5L

I/O6L

I/O7L

VCC

I/O8L

I/O9L

I/O0R

3332313029282726

CY7C038V (64K x 18)

[2]

[2]

Note

2. This pin is NC for CY7C037V/037AV.

(continued)

Figure 2. 100-Pin TQFP (Top View)

Selection Guide

Maximum Access Time 15 20 25 ns
Typical Operating Current 125 120 115 mA
Typical Standby Current for I
Typical Standby Current for I

Parameter -15 -20 -25 Unit

(Both ports TTL level) 35 35 30 mA

SB1

(Both ports CMOS level) 10 μA10 μA10 μA μA

SB3

Document #: 38-06078 Rev. *B Page 3 of 18

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CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Pin Definitions

Left Port Right Port Description

CE

, CE

0L

1L

R/W

L

OE

L

A

0L–A15L

I/O0L–I/O
SEM
UB
LB
INT
BUSY

17L

SEM

L

L

L

L

L

M/S
V

CC

GND Ground
NC No Connect

CE0R, CE
R/W

R

OE

R

A0R–A

15R

I/O0R–I/O

R

UB

R

LB

R

INT

R

BUSY

R

1R

17R

Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
Read/Write Enable
Output Enable
Address (A0–A14 for 32K; A0–A15 for 64K devices)
Data Bus Input/Output (I/O0–I/O15 for x16 devices; I/O0–I/O17 for x18)
Semaphore Enable
Upper Byte Select (I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices)
Lower Byte Select (I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power

Architecture

The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V consist of an array of 32K and 64K words
of 16 and 18 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE

, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same l ocatio n, a BUSY pin is
provided on each port. Two interrupt (INT
port-to-port communication. Two semaphore (SEM
used for allocating shared resources. With the M/S
function as a master (BUSY

pins are outputs) or as a slave (BUSY pins

) pins can be utilized for

) control pins are

pin, the devices can

are inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output enable
control (OE

), which allows data to be read from the d evice.

Functional Description

The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V are low power CMOS 32K, 64K x 16/18
dual-port static RAMs. V arious arbitration schemes are included
on the devices to handle situations when multiple processors
access the same piece of data. Two ports are provided, permit­ting independent, asynchronous access for read s and writes to
any location in memory. The devices can be utilized as
stand-alone 16/18-bit dual-port static RAMs or multiple devices
can be combined to function as a 32/36-bit or wider master/slave
dual-port static RAM. An M/S
32/36-bit or wider memory applications without the need for sep­arate master and slave devices or additional discrete logic. Ap­plication areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port video/graphics
memory.

Each port has independent control pins: chip enable (CE
or write enable (R/ W
on each port (BUSY

), and output enable (OE). T wo flags are provided

and INT). BUSY signals that the port is trying to
access the same location currently being accessed by the othe r port.
The interrupt flag (INT

) permits communication between ports or

pin is provided for implementing

), read

systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indi cate that a shared
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared re sou rce i s in use . An
automatic power down feature is controlle d independently on each port
by a chip select (CE

) pin.

The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V are available in 100-pin Thin Quad Plas­tic Flatpacks (TQFP).

Write Operation

Data must be set up for a duration of tSD before the rising edge of

to guarantee a valid write. A write operation is controlled by either

R/W
the R/W

pin (see Figure 7 ) or the CE pin (see Figure8). Required inputs

for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite port

attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
the data is presented on the other port.

DDD

after

Read Operation

When reading the device, the user must assert both the OE an d

pins. Data is available t

CE
the user wishes to access a semaphore flag, then the SEM
asserted instead of the CE

after CE or t

ACE

after OE is asserted. If

DOE

pin must be

pin, and OE must also be asserted.

Interrupts

The upper two memory locations may be used for message
passing. The highest memory location (7FFF for the
CY7C027V/027VN/027AV/37V, FFFF for the CY7C028V/38V) is
the mailbox for the right port and the second-highest memory
location (7FFE for the CY7C027V/027VN/027AV/037V/037AV,
FFFE for the CY7C028V/38V) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an interrupt is

Document #: 38-06078 Rev. *B Page 4 of 18

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CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.

Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.

The operation of the interrupts and their interaction with Busy are
summarized in Table 2.

Busy

The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CE

s are asserted and an address match occurs within tPS of each other,
the busy logic determines which port has access. If t
port definitely gains permission to the location, but it is not predictable
which port gets that permission. BUSY is asserted t
match or t

after CE is taken LOW.

BLC

is violated, one

PS

after an address

BLA

Master/Slave

A M/S pin is provided to expand the word width by configuring the
device as either a master or a sl ave. The BUSY
connected to the BUSY

input of the slave. This allows the device to

output of the master is

interface to a master device with no external components. Writing to
slave devices must be delayed until after the BUSY

or t

(t

BLC

a contention situation. When tied HIGH, the M/S

), otherwise, the slave chip may begin a write cycle during

BLA

to be used as a master and, therefore, the BUSY

input has settled

pin allows the device

line is an output. BUSY

can then be used to send the arbitration outcome to a slave.

Semaphore Operation

The CY7C027V/027VN/027AV/028V and
CY7037V/037AV/038V provide eight semaphore latches, which
are separate from the dual-port memory locations. Semaphores

are used to reserve resources that are shared be tween th e two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM
deasserted for t
semaphore value is available t
semaphore write. If the left port was successful (reads a zero), it

before attempting to read the semaphore. The

SOP

SWRD

+ t

after the rising edge of the

DOE

or OE must be

assumes control of the shared resource, otherwise (reads a one) it
assumes the right port has control and continues to poll the semaphore.
When the right side has relinquished control of the semaph ore (by
writing a one), the left side succeeds in gaining control of the
semaphore. If the left side no longer requires the semap hore, a one i s
written to cancel its request.

Semaphores are accessed by asserting SEM
functions as a chip select for the semaphore latches (CE
HIGH during SEM
and R/W are used in the same manner as a normal memory access.

LOW). A

represents the semaphore address. OE

0–2

LOW. The SEM pin

must remain

When writing or reading a semaphore, the other address pins have no
effect.

When writing to the semaphore, only I/O
to the left port of an available semaphore, a one appears at the same

is used. If a zero is written

0

semaphore address on the right port . That semaphore can now only be
modified by the side showing zero (the left port in this case). If the left
port now relinquishes control by writing a one to the semaphore, the
semaphore is set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while th e left port had control,
the right port would immediately own the semaphore as so on as the left
port released it. Table 3 shows sample semaphore operations.

When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to access
the semaphore within t
obtained by one side or the other, but there is no guarantee which side

of each other , the semaphore is definitely

SPS

controls the semaphore.

Document #: 38-06078 Rev. *B Page 5 of 18

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CY7C027V/027VN/027AV/028V

CY7C037V/037AV/038V

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested .

°

Storage Temperature .................................–65

Ambient Temperature with

Power Applied ............................................–55

Supply Voltage to Ground Potential................–0.5V to +4.6V

DC Voltage Applied to

Outputs in High-Z State...........................–0.5V to VCC+0.5V

C to +150°C

°

C to +125°C

DC Input Voltage

[2]

..................................–0.5V to VCC+0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 1100V

Latch-up Current.................................................... > 200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial

[3]

Ambient

Temperature V

CC

–40°C to +85°C 3.3V ± 300 mV

Electrical Characteristics

Over the Operating Range

Parameter Description

V

V
V
V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

OH

OL
IH
IL

Output HIGH Voltage
(V

=Min., IOH= –4.0 mA)

CC

Output LOW Voltage (VCC=Min., IOH= +4.0 mA) 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 2.2 2.2 V
Input LOW Voltage 0.8 0.8 0.8 V
Input Leakage Current −55−55−55μA
Output Leakage Current –10 10 –10 10 –10 10 μA
Operating Current (VCC=Max. I

mA) Outputs Disabled
Standby Current (Both Ports TTL

Level) CE

& CER ≥ VIH, f=f

L

Standby Current (One Port TTL Level)
CE

| CER ≥ VIH, f=f

L

MAX

Standby Current (Both Ports CMOS
Level) CE

& CER ≥ VCC−0.2V, f=0

L

Standby Current (One Port CMOS Lev-

| CER ≥ VIH, f=f

el) CE

L

MAX

MAX

[4]

OUT

CY7C027V/027VN/027AV/028V/CY7C037V/037AV/038V

Min Typ Max Min Typ Max Min Typ Max

2.4 2.4 2.4 V

=0

Com’l. 125 185 120 175 115 165 mA

[3]

Ind.

140 195 mA

Com’l. 35 50 35 45 30 40 mA

[3]

Ind.

45 55 mA

Com’l. 80 120 75 110 65 95 mA

[3]

Ind.

85 120 mA

Com’l. 10 250 10 250 10 250 μA

Ind.

[3]

10 250 μA

Com’l. 75 105 70 95 60 80 mA

[3]

Ind.

80 105 mA

Unit-15 -20 -25

Capacitance

[5]

Parameter Description Test Conditions Max Unit

C

IN

C

OUT

Notes

2. Pulse width < 20 ns.

3. Industrial parts are available in CY7C028V and CY7C038V only.

4. f

= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no addr ess or control line s change. This appli es only to input s at CMOS level st andby I

MAX

5. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-06078 Rev. *B Page 6 of 18

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V

Output Capacitance 10 pF

CC

10 pF

SB3

.

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