CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
Features
R/W
L
OE
L
IO
8/9L
–IO
15/17L
IO
Control
Address
Decode
A
0L–A11/12/13L
CE
L
OE
L
R/W
L
BUSY
L
IO
Control
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
UB
L
LB
L
IO0L–IO
7/8L
R/W
R
OE
R
IO
8/9L
–IO
15/17R
CE
R
UB
R
LB
R
IO0L–IO
7/8R
UB
L
LB
L
A0L–A
11/1213L
True Dual-Ported
RAM Array
A0R–A
11/12/13R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
UB
R
LB
R
Address
Decode
A
0R–A11/12/13R
[2]
[2]
[3]
[3]
[5]
[5]
12/13/14
8/9
8/9
12/13/14
8/9
8/9
12/13/14 12/13/14
[4]
[4]
[4]
[4]
Logic Block Diagram
■
True dual-ported memory cells which enable simultaneous
access of the same memory location
■
4, 8 or 16K × 16 organization
■
(CY7C024AV/024BV
■
4 or 8K × 18 organization (CY7C0241AV/0251AV)
■
16K × 18 organization (CY7C036AV)
■
0.35 micron CMOS for optimum speed and power
■
High speed access: 20 and 25 ns
■
Low operating power
❐
Active: ICC = 115 mA (typical)
❐
Standby: I
SB3
[1]
/ 025AV/026AV)
= 10 μA (typical)
■
Fully asynchronous operation
■
Automatic power down
■
Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
■
On chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper byte and lower byte control
■
Pin select for Master or Slave (M/S)
■
Commercial and industrial temperature ranges
■
Available in 100-pin Pb-free TQFP and 100-pin TQFP
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO
3. IO
4. A
5. BUSY
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06052 Rev. *J Revised December 10, 2008
–IO15 for x16 devices; IO9–IO17 for x18 devices.
8
–IO7 for x16 devices; IO0–IO8 for x18 devices.
0
for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
0–A11
is an output in master mode and an input in slave mode.
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
NC
NC
IO
10L
IO
11L
IO
15L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/S
BUSY
R
IO
14L
GND
IO
12L
IO
13L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 4748
49 50
IO9LIO8LIO7LIO6LIO5LIO4LIO3LIO
2L
GND
IO
1LIO0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
NC
A
11LA10L
A9LA8LA7LA
6L
IO
0R
IO7RIO8RIO
9R
IO
10RIO11RIO12RIO13RIO14R
GND
IO
15R
Œ
R
R\W
R
GND
SEM
RCERUBRLBR
NC
A
11RA10R
A9RA8RA7RA6RA
5R
CY7C024AV/024BV (4K × 16)
R/
W
L
[6]
[7]
CY7C025AV (8K × 16)
Pin Configurations
Figure 1. 100-Pin TQFP (Top View)
Notes
on the CY7C025AV.
6. A
12L
7. A
on the CY7C025AV.
12R
Document #: 38-06052 Rev. *J Page 2 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
IO
11L
IO
12L
IO
16L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/
S
BUSY
R
IO
15L
GND
IO
13L
IO
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48
49 50
IO9LIO7LIO6LIO5LIO4LIO3LIO
2L
IO
10L
GND
IO
1LIO0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
NC
A
11LA10L
A9LA8LA7LA
6L
IO
0R
IO
7R
IO
16R
IO
9R
IO
10RIO11RIO12RIO13RIO14R
GND
IO
15R
OE
R
R/
W
R
GND
SEM
RCERUBRLBR
NC
A
11RA10R
A9RA8RA7RA6RA
5R
CY7C0241AV (4K × 18)
IO
8L
IO
17L
IO
8R
IO
17R
R/
W
L
[9]
[8]
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
NC
A6L
A5L
A4L
INT
L
A2L
A0L
GND
M/
S
A0R
A1R
A1L
A3L
BUSY
R
INT
R
A2R
A3R
A4R
A5R
NC
NC
NC
BUSY
L
58
57
56
55
54
53
52
51
CY7C026AV (16K × 16)
NC
NC
NC
NC
IO10L
IO11L
IO15L
IO13L
IO14L
GND
IO0R
VCC
IO3R
GND
IO12L
IO1R
IO2R
IO4R
IO5R
IO6R
NC
NC
NC
NC
VCC
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
IO9L
IO8L
IO7L
IO6L
IO5L
IO4L
IO0L
IO2L
IO1L
VCC
R/
WL
UBLLB
L
GND
IO3L
SEMLCELA13L
A12L
A11L
A10L
A9L
A8L
A7L
OE
L
34 35 36 424139 403837 43 44 45 5048 494746
A6R
A7R
A8R
A9R
A10R
A11R
CE
R
A13R
UB
R
GND
R/
WR
GND
IO14R
LB
R
A12R
OE
R
IO15R
IO13R
IO12R
IO11R
IO10R
IO9R
IO8R
IO7R
SEM
R
3332313029282726
CY7C0251AV (8K × 18)
(continued)
Figure 2. 100-Pin TQFP (Top View)
Notes
on the CY7C0251AV.
8. A
12L
on the CY7C0251AVC.
9. A
12R
Document #: 38-06052 Rev. *J Page 3 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
IO
11L
IO
12L
IO
16L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/S
BUSY
R
IO
15L
GND
IO
13L
IO
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 8180 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 4748 49 50
IO9LIO7LIO6LIO5LIO4LIO3LIO
2L
IO
10L
GND
IO
1LIO0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
A
11LA10L
A9LA8LA7LA
6L
IO
0R
IO
7R
IO
16R
IO
9R
IO
10RIO11RIO12RIO13RIO14R
GND
IO
15R
OE
R
R/W
R
GND
SEM
RCERUBRLBR
A
11RA10R
A9RA8RA7RA6RA
5R
IO
8L
IO
17L
IO
8R
IO
17R
R/W
L
CY7C036AV (16K × 18)
A
13L
A
13R
A
12L
A
12R
(continued)
Figure 3. 100-Pin TQFP (Top View)
Selection Guide
Parameter
CY7C0241AV/0251AV/036AV
-20
CY7C024AV/024BV/025AV/026AV
Maximum Access Time 20 25 ns
Typical Operating Current 120 1 15 mA
Typical Standby Current for I
(Both ports TTL Level)
Typical Standby Current for I
(Both ports CMOS Level)
Document #: 38-06052 Rev. *J Page 4 of 19
SB1
SB3
35 30 mA
10 10 μA
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-25
Unit
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port Right Port Description
CE
L
R/W
L
OE
L
A
0L–A13L
–IO
IO
0L
17L
SEM
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A0R–A
IO0R–IO
R
UB
R
LB
R
INT
R
BUSY
R
13R
17R
M/S
V
CC
GND Ground
NC No Connect
Chip Enable
Read and Write Enable
Output Enable
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K)
Data Bus Input and Output
Semaphore Enable
Upper Byte Select (IO8–IO15 for x16 devices; IO9–IO17 for x18 devices)
Lower Byte Select (IO0–IO7 for x16 devices; IO0–IO8 for x18 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Architecture
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and
16K words of 16 and 18 bits each of dual-port RAM cells, IO and
address lines, and control signals (CE
, OE, RW). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes and reads to the same
location, a BUSY
pin is provided on each port. Two Interrupt (INT)
pins can be used for port to port communication. Two Semaphore
(SEM) control pins are used for allocating shared resources. With
the M/S
outputs) or as a slave (BUSY
automatic power down feature controlled by CE
own output enable control (OE
pin, the devices can function as a master (BUSY pins are
pins are inputs). They also have an
. Each port has its
), which enables data to be read from
the device.
Functional Description
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and
16K ×16/18 dual port static RAMs. V arious arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. There are two ports
permitting independent, asynchronous access for reads and writes
to any location in memory. The devices can be used as standalone
16 or18-bit dual port static RAMs or multiple devices can be
combined to function as a 32 or 36-bit or wider master and slave
dual port static RAM. An M/S
36-bit or wider memory applications. It does not need separate
master and slave devices or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communications status buffering, and dual port video and graphics memory.
Each port has independent control pins: Chip Enable (CE
or Write Enable (R/W
provided on each port (BUSY
port is trying to access the same location currently being
pin is provided for implementing 32 or
), Read
), and Output Enable (OE). Two flags are
and INT). BUSY signals that the
accessed by the other port. The Interrupt flag (INT
) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic has eight shared l atches. Only one side can
control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Select (CE
) pin.
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV0251AV/036A V are available in 100-pin Pb-free Thin
Quad Flat Pack (TQFP) and 100-pin TQFP .
Write Operation
Data must be set up for a duration of tSD before the rising edge
of RW
to guarantee a valid write. A write operation is controlled
by either the RW
pin (see Figure 8 on page 12) or the CE pin (see
Figure 9 on page 12). Required inputs for non-contention opera-
tions are summarized in Table 1 on page 7.
If a location is being written to by one port and the opposite port
tries to read that location, there must be a port to port flowthrough
delay before the data is read on the output; otherwise the d ata
read is not deterministic. Data is valid on the port t
data is presented on the other port.
DDD
after the
Read Operation
When reading the device, the user must assert both the OE and
pins. Data is available t
CE
asserted. If the user wants to access a semaphore flag, then the
SEM
pin and OE must be asserted.
after CE or t
ACE
after OE is
DOE
Interrupts
The upper two memory locations are for message passing. The
highest memory location (FFF for the
CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
Document #: 38-06052 Rev. *J Page 5 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3FFF for the CY7C026AV/36AV) is the mailbox for the right port
and the second highest memory location (FFE for the
CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV,
3FFE for the CY7C026AV/36AV) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an inte rrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2 on page 7.
Busy
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036A V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CE
s are asserted and an address match occurs within tPS of each
other, the busy logic determines which port has access. If t
violated, one port definitely gains permission to the location, but it is
not predictable which port gets that permission. BUSY
after an address match or t
t
BLA
after CE is taken LOW.
BLC
is asserted
PS
is
Master/Slave
A M/S pin helps to expand the word width by configuring the
device as a master or a slave. The BUSY
connected to the BUSY
input of the slave. This enables the
device to interface to a master device with no external components. Writing to slave devices must be delayed until after the
BUSY
input has settled (t
may begin a write cycle during a contention situation. When tied
BLC
or t
BLA
HIGH, the M/S pin enables the device to be u sed as a master
and, therefore, the BUSY
line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
output of the master is
). Otherwise, the slave chip
Semaphore Operation
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036A V provide eight semaphore latches,
which are separate from the dual port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM
be deasserted for t
The semaphore value is available t
edge of the semaphore write. If the left port was successful
before attempting to read the semaphore.
SOP
SWRD
+ t
(reads a zero), it assumes control of the shared resource.
Otherwise (reads a one), it assumes the right port has con trol
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side succeeds in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE
and RW are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only IO
written to the left port of an available semaphore, a one appears
is used. If a zero is
0
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. T able 3 on page 7 shows sample semaphore
operations.
When reading a semaphore, all 16 and 18 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
obtained by one of them. But there is no guarantee which side
of each other, the semaphore is definitely
SPS
controls the semaphore.
or OE must
after the rising
DOE
LOW. The SEM
represents the
0–2
Document #: 38-06052 Rev. *J Page 6 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Table 1. Non-Contending Read/Write
Inputs Outputs
CE R/W OE UB LB SEM IO9–IO
17
IO0–IO
8
Operation
H X X X X H High Z High Z Deselected: Power Down
X X X H H H High Z High Z Deselected: Power Down
L L X L H H Data In High Z Write to Upper Byte Only
L L X H L H High Z Data In Write to Lower Byte Only
L L X L L H Data In Data In Write to Both Bytes
L H L L H H Data Out High Z Read Upper Byte Only
L H L H L H High Z Data Out Read Lower Byte Only
L H L L L H Data Out Data Out Read Both Bytes
X X H X X X High Z High Z Outputs Disabled
H H L X X L Data Out Data Out Re ad Data in Semaphore Fl ag
X H L H H L Data Out Data Out Read Data in Semaphore Flag
H X X X L Data In Data In Write D
X X H H L Data In Data In Write D
into Semaphore Flag
IN0
into Semaphore Flag
IN0
L X X L X L Not Allowed
L X X X L L Not Allowed
Table 2. Interrupt Operation Example (assu mes BUSY
= BUSYR = HIGH)
L
[10]
Left Port Right Port
Function R/WLCELOE
L
Set Right INTR Flag L L X FFF
A
0L–13L
[13]
XXXX X L
INTLR/WRCEROE
R
A
0R–13R
INT
Reset Right INTR Flag X X X X X X L L FFF (or 1/3FFF) H
Set Left INTL Flag XXX X L
Reset Left INT
Flag X L L 1FFE
L
[13]
H
[11]
[12]
L L X 1FFE (or 1/3FFE) X
XXX X X
Table 3. Semaphore Operation Exam ple
Function IO0–IO
Left IO0–IO
17
Right Status
17
No action 1 1 Semaphore-free
Left port writes 0 to semaphore 0 1 Left Port has semaphore token
Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore
Left port writes 1 to semaphore 1 0 Right port obtains semaphore token
Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore
Right port writes 1 to semaphore 0 1 Left port obtains semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Right port writes 0 to semaphore 1 0 Right port has semaphore token
Right port writes 1 to semaphore 1 1 Semaphore free
Left port writes 0 to semaphore 0 1 Left port has semaphore token
Left port writes 1 to semaphore 1 1 Semaphore-free
Notes
10.See Functional Description on page 5 for specific highest memory locations by device.
11. If BUSY
12. If BUSY
13.See Functional Description on page 5 for specific addresses by device.
=L, then no change.
R
=L, then no change.
L
R
[12]
[11]
Document #: 38-06052 Rev. *J Page 7 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Maximum Ratings
Exceeding maximum ratings
device. User guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State .........................–0.5V to V
[14]
may shorten the useful life of the
+ 0.5V
CC
Electrical Characteristics
Over the Operating Range
Parameter Description
V
V
V
V
I
OZ
I
IX
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
OH
OL
IH
IL
Output HIGH Voltage (VCC=3.3V) 2.4 2.4 V
Output LOW Voltage 0.4 0.4 V
Input HIGH Voltage 2.0 2.0 V
Input LOW Voltage –0.3
Output Leakage Current –10 10 –10 10 μA
Input Leakage Current –10 10 –10 10 μA
Operating Current (V
I
= 0 mA) Outputs Disabled
OUT
CC
= Max.,
Standby Current (Both Ports TTL Level)
CE
& CER ≥ VIH, f = f
L
MAX
Standby Current (One Port TTL Level)
CE
| CER ≥ VIH, f = f
L
MAX
Standby Current (Both Ports CMOS Level)
CE
& CER ≥ VCC−0.2V, f = 0
L
Standby Current (One Port CMOS Level)
CE
| CER ≥ VIH, f = f
L
MAX
[18]
DC Input Voltage
...............................–0.5V to V
CC
+ 0.5V
[15]
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial
[16]
–40°C to +85°C 3.3V ± 300 mV
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20 -25
Min Typ Max Min Typ Max
[17]
0.8 0.8 V
Com’l. 120 175 115 165 mA
Ind.
[16]
135 185 mA
Com’l. 35 45 30 40 mA
Ind.
[16]
40 50 mA
Com’l. 75 110 65 95 mA
Ind.
[16]
75 105 mA
Com’l. 10 500 10 500 μA
Ind.
[16]
10 500 μA
Com’l. 70 95 60 80 mA
Ind.
[16]
70 90 mA
CC
Unit
Capacitance
SB3
[19]
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
.
Description Test Conditions Max Unit
10 pF
V
= 3.3V
CC
Parameter
C
IN
C
OUT
Notes
14.The voltage on any input or IO pin cannot exceed the power pin during power up.
15.Pulse width < 20 ns.
16.Industrial parts are available in CY7C026AV and CY7C036AV only.
–1.5V for pulse width less than 10ns.
17.VIL >
= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
18.f
MAX
standby I
19.Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06052 Rev. *J Page 8 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Figure 4. AC Test Loads and Waveforms
3.0V
GND
90%
90%
10%
3ns
3
ns
10%
ALL INPUTPULSES
(a) Normal Load (Load
1)
R1 = 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30
pF
V
TH
=1.4V
OUTPUT
C=
30pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay(Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
R
TH
= 250Ω
≤
≤
including scope and jig)
(Used for t
LZ
, tHZ, t
HZWE
, and t
LZWE
Switching Characteristics
Over the Operating Range
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
[21]
t
ACE
t
DOE
[22, 23, 24]
t
LZOE
[22, 23, 24]
t
HZOE
[22, 23, 24]
t
LZCE
[22, 23, 24]
t
HZCE
[24]
t
PU
[24]
t
PD
[21]
t
ABE
Write Cycle
t
WC
[21]
t
SCE
t
AW
t
HA
[21]
t
SA
Notes
20.Test conditions assume signal transition time of 3 ns or less, timing referen ce levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the speci fie d I
and 30 pF load capacitance.
21.To access RAM, CE
22.At any given temperature and voltage condition for any given device, t
23.Test conditions used are Load 3.
24.This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
Document #: 38-06052 Rev. *J Page 9 of 19
[20]
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20 -25
Min Max Min Max
Read Cycle Time 20 25 ns
Address to Data Valid 20 25 ns
Output Hold From Address Change 3 3 ns
CE LOW to Data Valid 20 25 ns
OE LOW to Data Valid 12 13 ns
OE Low to Low Z 3 3 ns
OE HIGH to High Z 12 15 ns
CE LOW to Low Z 3 3 ns
CE HIGH to High Z 12 15 ns
CE LOW to Power Up 0 0 ns
CE HIGH to Power Down 20 25 ns
Byte Enable Access Time 20 25 ns
Write Cycle Time 20 25 ns
CE LOW to Write End 15 20 ns
Address Valid to Write End 15 20 ns
Address Hold From Write End 0 0 ns
Address Setup to Write Start 0 0 ns
= L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
time.
SCE
Unit
OI/IOH
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Characteristics
Data Retention Mode
3.0V
3.0V
V
CC
> 2.0V
V
CC
to VCC– 0.2V
V
CC
CE
t
RC
V
IH
Over the Operating Range (continued)
Parameter Description
t
PWE
t
SD
t
HD
[23, 24]
t
HZWE
[23, 24]
t
LZWE
[25]
t
WDD
[25]
t
DDD
Busy Timing
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
[27]
t
BDD
Interrupt Timing
t
INS
t
INR
Write Pulse Width 15 20 ns
Data Setup to Write End 15 15 ns
Data Hold From Write End 0 0 ns
R/W LOW to High Z 12 15 ns
R/W HIGH to Low Z 3 0 ns
Write Pulse to Data Delay 45 50 ns
Write Data Valid to Read Data Valid 30 35 ns
[26]
BUSY LOW from Address Match 20 20 ns
BUSY HIGH from Address Mismatch 20 20 ns
BUSY LOW from CE LOW 20 20 ns
BUSY HIGH from CE HIGH 17 17 ns
Port Setup for Priority 5 5 ns
R/W HIGH after BUSY (Slave) 0 0 ns
R/W HIGH after BUSY HIGH (Slave) 15 17 ns
BUSY HIGH to Data Valid 20 25 ns
[26]
INT Set Time 20 20 ns
INT Reset Time 20 20 ns
Semaphore Timing
t
SOP
t
SWRD
t
SPS
t
SAA
SEM Flag Update Pulse (OE or SEM)1012ns
SEM Flag Write to Read Time 5 5 ns
SEM Flag Contention Window 5 5 ns
SEM Address Access Time 20 25 ns
[20]
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-20 -25
Min Max Min Max
Unit
Data Retention Mode
Timing
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV are designed for battery backup.
Data retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
1. Ch ip Enable (CE) must be held HIGH during data retention,
within V
2. CE
to VCC – 0.2V.
CC
must be kept between VCC – 0.2V and 70 percent of VCC
during the power up and power down transitions.
3. The RAM can begin operation >t
minimum operating voltage (3.0V).
Notes
25.For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
26.Test conditions used are Load 2.
27.t
28.CE
Document #: 38-06052 Rev. *J Page 10 of 19
is a calculated parameter and is the greater of t
BDD
= VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
after VCC reaches the
RC
– t
PWE
(actual) or t
WDD
[28]
– tSD (actual).
DDD
Parameter Test Conditions
ICC
DR1
at VCCDR = 2V 50 μA
Max Unit
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
OHA
Figure 5. Read Cycle No. 1 (Either Port Address Access)
[29, 30, 31]
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
t
LZCE
t
PU
t
PD
I
SB
I
CC
DATA OUT
OE
CE and
LB
or UB
CURRENT
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)
[29, 32, 33]
UB or LB
DATAOUT
t
RC
ADDRESS
t
AA
t
OHA
CE
t
LZCE
t
ABE
t
HZCE
t
HZCE
t
ACE
t
LZCE
Figure 7. Read Cycle No. 3 (Either Port)
[29, 31, 32, 33]
Notes
29.R/W
is HIGH for read cycles.
30.Device is continuously selected CE
= VIL.
31.OE
32.Address valid prior to or coincident with CE
33.To access RAM, CE
Document #: 38-06052 Rev. *J Page 11 of 19
= VIL, UB or LB = VIL, SEM = VIH. T o access semaphore, CE = VIH, SEM = VIL.
= VIL and UB or LB = VIL. This waveform cannot be used for semaphor e reads.
transition LOW.
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATAOUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
Figure 8. Write Cycle No. 1: R/W Controlled Timing
[34, 35, 36, 37]
[40]
[40]
[37]
[38, 39]
NOTE 41
NOTE 41
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
Figure 9. Write Cycle No. 2: CE Controlled Timing
[34, 35, 36, 42]
[38, 39]
(continued)
Notes
or CE must be HIGH during all address transitions.
34.R/W
35.A write occurs during the overlap (t
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
36.t
HA
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
37.If OE
data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does no t apply and the write pulse can
be as short as the specified t
38.To access RAM, CE
39.To access upper byte, CE
To access lower byte, CE
40.Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent test ed.
41.During this period, the IO pins are in the output state, and input signals must not be applied.
42.If the CE
= VIL, SEM = VIH.
or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
SCE
.
PWE
= VIL, UB = VIL, SEM = VIH.
= VIL, LB = VIL, SEM = VIH.
Document #: 38-06052 Rev. *J Page 12 of 19
or t
) of a LOW CE or SEM and a LOW UB or LB.
PWE
or (t
PWE
+ tSD) to enable the IO drivers to turn off and
HZWE
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
t
SOP
t
SAA
VALID ADRESS VALID ADRESS
t
HD
DATAINVALID
DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
OE
R/W
IO
0
SEM
A0–A
2
Figure 10. Semaphore Read After Write Timing, Either Side
[43]
MATCH
t
SPS
A0L–A
2L
MATCH
R/W
L
SEM
L
A0R–A
2R
R/W
R
SEM
R
Figure 11. Timing Diagram of Semaphore Contention
[44, 45, 46]
(continued)
Notes
= HIGH for the duration of the above timing (both write and read cycle).
43.CE
= IO0L = LOW (request semaphore); CER = CEL = HIGH.
44.IO
0R
45.Semaphores are reset (available t o both ports) at cycle start.
46.If t
is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
SPS
Document #: 38-06052 Rev. *J Page 13 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA IN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
Figure 12. Timing Diagram of Read with BUSY (M/S=HIGH)
[47]
t
PWE
R/W
BUSY
t
WB
t
WH
Figure 13. Write Timing with Busy Input (M/S=LOW)
(continued)
Note
47.CE
= CER = LOW.
L
Document #: 38-06052 Rev. *J Page 14 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CERValidFirst:
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
Figure 14. Busy Timing Diagram No.1 (CE Arbitration)
[48]
CELValid First
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
tRCor t
WC
t
BLA
t
BHA
ADDRESS
R
Right Address Valid First:
Figure 15. Busy Timing Diagram No.2 (Address Arbitration)
[48]
Left Address Valid First:
(continued)
Note
is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
48.If t
PS
Document #: 38-06052 Rev. *J Page 15 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
WRITE 1FFF (OR 1/3FFF)
t
WC
Right SideClearsINTR:
t
HA
READ 7FFF
t
RC
t
INR
WRITE 1FFE (OR 1/3FFE)
t
WC
Right Side Sets INT
L
:
Left Side Sets INT
R
:
Left SideClears INT
L
:
READ 7FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
t
HA
t
INS
(OR 1/3FFF)
OR 1/3FFE)
[49]
[50]
[50]
[50]
[49]
[50]
Figure 16. Interrupt Timing Diagram
(continued)
Notes
depends on which enable pin (CEL or R/WL) is deasserted first.
49.t
HA
or t
50.t
INS
depends on which enable pin (CEL or R/WL) is asserted last.
INR
Document #: 38-06052 Rev. *J Page 16 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Ordering Information
4K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
15 CY7C0 24AV-15AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
20 CY7C0 24AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
25 CY7C0 24AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
Ordering Code
CY7C024BV-15AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C024AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C024AV-20AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C024AV-20AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C024AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C024AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C024AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
8K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
20 CY7C0 25AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C025AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C025AV-20AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial
25 CY7C0 25AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C025AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C025AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C025AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
16K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
20 CY7C0 26AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C026AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C026AV-20AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack Industrial
25 CY7C0 26AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C026AV-25AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
CY7C026AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
CY7C026AV-25AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack
4K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
20 CY7C0 241AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
25 CY7C0 241AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
8K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
20 CY7C0 251AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
25 CY7C0 251AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
Package
Diagram
Package
Name Package Type
Package
Name Package Type
Package
Name Package Type
Package
Name Package Type
Package Type
Operating
Range
Operating
Range
Operating
Range
Operating
Range
Operating
Range
Document #: 38-06052 Rev. *J Page 17 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
16K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code
20 CY7C0 36AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
25 CY7C0 36AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial
CY7C036AV-25AXC 51-85048 100-Pin Pb-free Thin Quad Flat Pack
CY7C036AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial
Package
Name Package Type
Package Diagram
Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
Operating
Range
51-85048 *C
Document #: 38-06052 Rev. *J Page 18 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document History Page
Document Title: CY7C024AV/024BV/025A V/026A V , CY7C0241A V/0251A V/036A V 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Document Number: 38-06052
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
** 1 10204 SZV 1 1 /11/01 Change from Spec number: 38-00838 to 38-06052
*A 122302 RBI 12/27/02 Power up requirements added to Maximum Ratings Information
*B 128958 JFU 9/03/03 Added CY7C025AV-25AI to Ordering Information
*C 237622 YDT See ECN Removed cross information from features section
*D 241968 WWZ See ECN Added CY7C024AV-25AI to Ordering Information
*E 276451 SPN See ECN Corrected x18 for 026AV to x16
*F 279452 RUY See ECN Added Pb-free packaging information
Corrected pin A113L to A13L on CY7C026AV pin list
Added minimum V
of 0.3V and note 16
IL
*G 373580 RUY See ECN Corrected CY7C024AC-25AXC to CY7C024AV -25AXC in Ordering Information
*H 380476 PCX See ECN Added to Part Ordering information:
CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI,
CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI
*I 2543577 NXR/AESA 07/25/08 Updated note number 33 on page 12 from “R/W
address transitions” to “R/W
or CE must be HIGH during all address transitions”
must be HIGH during all
*J 2623540 VKN/PYRS 12/17/08 Added CY7C024BV part
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integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spec ified above is p rohibited with out
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cy press does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
Document #: 38-06052 Rev. *J Revised December 10, 2008 Page 19 of 19
All products and company names mention ed in this document may be the trademarks of their respective holders.
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