CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
Features
R/W
L
OE
L
IO
8/9L
–IO
15/17L
IO
Control
Address
Decode
A
0L–A11/12/13L
CE
L
OE
L
R/W
L
BUSY
L
IO
Control
CE
L
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
UB
L
LB
L
IO0L–IO
7/8L
R/W
R
OE
R
IO
8/9L
–IO
15/17R
CE
R
UB
R
LB
R
IO0L–IO
7/8R
UB
L
LB
L
A0L–A
11/1213L
True Dual-Ported
RAM Array
A0R–A
11/12/13R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
UB
R
LB
R
Address
Decode
A
0R–A11/12/13R
[2]
[2]
[3]
[3]
[5]
[5]
12/13/14
8/9
8/9
12/13/14
8/9
8/9
12/13/14 12/13/14
[4]
[4]
[4]
[4]
Logic Block Diagram
■
True dual-ported memory cells which enable simultaneous
access of the same memory location
■
4, 8 or 16K × 16 organization
■
(CY7C024AV/024BV
■
4 or 8K × 18 organization (CY7C0241AV/0251AV)
■
16K × 18 organization (CY7C036AV)
■
0.35 micron CMOS for optimum speed and power
■
High speed access: 20 and 25 ns
■
Low operating power
❐
Active: ICC = 115 mA (typical)
❐
Standby: I
SB3
[1]
/ 025AV/026AV)
= 10 μA (typical)
■
Fully asynchronous operation
■
Automatic power down
■
Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
■
On chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper byte and lower byte control
■
Pin select for Master or Slave (M/S)
■
Commercial and industrial temperature ranges
■
Available in 100-pin Pb-free TQFP and 100-pin TQFP
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO
3. IO
4. A
5. BUSY
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06052 Rev. *J Revised December 10, 2008
–IO15 for x16 devices; IO9–IO17 for x18 devices.
8
–IO7 for x16 devices; IO0–IO8 for x18 devices.
0
for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
0–A11
is an output in master mode and an input in slave mode.
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
NC
NC
IO
10L
IO
11L
IO
15L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/S
BUSY
R
IO
14L
GND
IO
12L
IO
13L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 4748
49 50
IO9LIO8LIO7LIO6LIO5LIO4LIO3LIO
2L
GND
IO
1LIO0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
NC
A
11LA10L
A9LA8LA7LA
6L
IO
0R
IO7RIO8RIO
9R
IO
10RIO11RIO12RIO13RIO14R
GND
IO
15R
Œ
R
R\W
R
GND
SEM
RCERUBRLBR
NC
A
11RA10R
A9RA8RA7RA6RA
5R
CY7C024AV/024BV (4K × 16)
R/
W
L
[6]
[7]
CY7C025AV (8K × 16)
Pin Configurations
Figure 1. 100-Pin TQFP (Top View)
Notes
on the CY7C025AV.
6. A
12L
7. A
on the CY7C025AV.
12R
Document #: 38-06052 Rev. *J Page 2 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
40
39
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
IO
11L
IO
12L
IO
16L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/
S
BUSY
R
IO
15L
GND
IO
13L
IO
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 81 80 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 47 48
49 50
IO9LIO7LIO6LIO5LIO4LIO3LIO
2L
IO
10L
GND
IO
1LIO0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
NC
A
11LA10L
A9LA8LA7LA
6L
IO
0R
IO
7R
IO
16R
IO
9R
IO
10RIO11RIO12RIO13RIO14R
GND
IO
15R
OE
R
R/
W
R
GND
SEM
RCERUBRLBR
NC
A
11RA10R
A9RA8RA7RA6RA
5R
CY7C0241AV (4K × 18)
IO
8L
IO
17L
IO
8R
IO
17R
R/
W
L
[9]
[8]
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
NC
A6L
A5L
A4L
INT
L
A2L
A0L
GND
M/
S
A0R
A1R
A1L
A3L
BUSY
R
INT
R
A2R
A3R
A4R
A5R
NC
NC
NC
BUSY
L
58
57
56
55
54
53
52
51
CY7C026AV (16K × 16)
NC
NC
NC
NC
IO10L
IO11L
IO15L
IO13L
IO14L
GND
IO0R
VCC
IO3R
GND
IO12L
IO1R
IO2R
IO4R
IO5R
IO6R
NC
NC
NC
NC
VCC
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
IO9L
IO8L
IO7L
IO6L
IO5L
IO4L
IO0L
IO2L
IO1L
VCC
R/
WL
UBLLB
L
GND
IO3L
SEMLCELA13L
A12L
A11L
A10L
A9L
A8L
A7L
OE
L
34 35 36 424139 403837 43 44 45 5048 494746
A6R
A7R
A8R
A9R
A10R
A11R
CE
R
A13R
UB
R
GND
R/
WR
GND
IO14R
LB
R
A12R
OE
R
IO15R
IO13R
IO12R
IO11R
IO10R
IO9R
IO8R
IO7R
SEM
R
3332313029282726
CY7C0251AV (8K × 18)
(continued)
Figure 2. 100-Pin TQFP (Top View)
Notes
on the CY7C0251AV.
8. A
12L
on the CY7C0251AVC.
9. A
12R
Document #: 38-06052 Rev. *J Page 3 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations
100 99 9798 96
2
3
1
4241
59
60
61
12
13
15
14
16
4
5
4039
95 94
17
26
9
10
8
7
6
11
27 28 3029 31 32 3534 36 37 3833
67
66
64
65
63
62
68
69
70
75
73
74
72
71
89 88 8687 8593 92 84
NC
NC
NC
A
5L
A
4L
INT
L
A
2L
A
0L
BUSY
L
GND
INT
R
A
0R
A
1L
NC
NC
IO
11L
IO
12L
IO
16L
V
CC
GND
IO
1R
IO
2R
V
CC
9091
A
3L
M/S
BUSY
R
IO
15L
GND
IO
13L
IO
14L
A
1R
A
2R
A
3R
A
4R
NC
NC
NC
IO
3R
IO
4R
IO
5R
IO
6R
NC
NC
18
19
20
21
22
23
24
25
83 82 8180 79 78 77 76
58
57
56
55
54
53
52
51
43 44 45 46 4748 49 50
IO9LIO7LIO6LIO5LIO4LIO3LIO
2L
IO
10L
GND
IO
1LIO0L
OE
L
SEM
L
V
CC
CE
L
UBLLB
L
A
11LA10L
A9LA8LA7LA
6L
IO
0R
IO
7R
IO
16R
IO
9R
IO
10RIO11RIO12RIO13RIO14R
GND
IO
15R
OE
R
R/W
R
GND
SEM
RCERUBRLBR
A
11RA10R
A9RA8RA7RA6RA
5R
IO
8L
IO
17L
IO
8R
IO
17R
R/W
L
CY7C036AV (16K × 18)
A
13L
A
13R
A
12L
A
12R
(continued)
Figure 3. 100-Pin TQFP (Top View)
Selection Guide
Parameter
CY7C0241AV/0251AV/036AV
-20
CY7C024AV/024BV/025AV/026AV
Maximum Access Time 20 25 ns
Typical Operating Current 120 1 15 mA
Typical Standby Current for I
(Both ports TTL Level)
Typical Standby Current for I
(Both ports CMOS Level)
Document #: 38-06052 Rev. *J Page 4 of 19
SB1
SB3
35 30 mA
10 10 μA
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
-25
Unit
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port Right Port Description
CE
L
R/W
L
OE
L
A
0L–A13L
–IO
IO
0L
17L
SEM
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A0R–A
IO0R–IO
R
UB
R
LB
R
INT
R
BUSY
R
13R
17R
M/S
V
CC
GND Ground
NC No Connect
Chip Enable
Read and Write Enable
Output Enable
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K)
Data Bus Input and Output
Semaphore Enable
Upper Byte Select (IO8–IO15 for x16 devices; IO9–IO17 for x18 devices)
Lower Byte Select (IO0–IO7 for x16 devices; IO0–IO8 for x18 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Architecture
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and
16K words of 16 and 18 bits each of dual-port RAM cells, IO and
address lines, and control signals (CE
, OE, RW). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes and reads to the same
location, a BUSY
pin is provided on each port. Two Interrupt (INT)
pins can be used for port to port communication. Two Semaphore
(SEM) control pins are used for allocating shared resources. With
the M/S
outputs) or as a slave (BUSY
automatic power down feature controlled by CE
own output enable control (OE
pin, the devices can function as a master (BUSY pins are
pins are inputs). They also have an
. Each port has its
), which enables data to be read from
the device.
Functional Description
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and
16K ×16/18 dual port static RAMs. V arious arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. There are two ports
permitting independent, asynchronous access for reads and writes
to any location in memory. The devices can be used as standalone
16 or18-bit dual port static RAMs or multiple devices can be
combined to function as a 32 or 36-bit or wider master and slave
dual port static RAM. An M/S
36-bit or wider memory applications. It does not need separate
master and slave devices or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communications status buffering, and dual port video and graphics memory.
Each port has independent control pins: Chip Enable (CE
or Write Enable (R/W
provided on each port (BUSY
port is trying to access the same location currently being
pin is provided for implementing 32 or
), Read
), and Output Enable (OE). Two flags are
and INT). BUSY signals that the
accessed by the other port. The Interrupt flag (INT
) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic has eight shared l atches. Only one side can
control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Select (CE
) pin.
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV0251AV/036A V are available in 100-pin Pb-free Thin
Quad Flat Pack (TQFP) and 100-pin TQFP .
Write Operation
Data must be set up for a duration of tSD before the rising edge
of RW
to guarantee a valid write. A write operation is controlled
by either the RW
pin (see Figure 8 on page 12) or the CE pin (see
Figure 9 on page 12). Required inputs for non-contention opera-
tions are summarized in Table 1 on page 7.
If a location is being written to by one port and the opposite port
tries to read that location, there must be a port to port flowthrough
delay before the data is read on the output; otherwise the d ata
read is not deterministic. Data is valid on the port t
data is presented on the other port.
DDD
after the
Read Operation
When reading the device, the user must assert both the OE and
pins. Data is available t
CE
asserted. If the user wants to access a semaphore flag, then the
SEM
pin and OE must be asserted.
after CE or t
ACE
after OE is
DOE
Interrupts
The upper two memory locations are for message passing. The
highest memory location (FFF for the
CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
Document #: 38-06052 Rev. *J Page 5 of 19
[+] Feedback
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3FFF for the CY7C026AV/36AV) is the mailbox for the right port
and the second highest memory location (FFE for the
CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV,
3FFE for the CY7C026AV/36AV) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an inte rrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2 on page 7.
Busy
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036A V provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CE
s are asserted and an address match occurs within tPS of each
other, the busy logic determines which port has access. If t
violated, one port definitely gains permission to the location, but it is
not predictable which port gets that permission. BUSY
after an address match or t
t
BLA
after CE is taken LOW.
BLC
is asserted
PS
is
Master/Slave
A M/S pin helps to expand the word width by configuring the
device as a master or a slave. The BUSY
connected to the BUSY
input of the slave. This enables the
device to interface to a master device with no external components. Writing to slave devices must be delayed until after the
BUSY
input has settled (t
may begin a write cycle during a contention situation. When tied
BLC
or t
BLA
HIGH, the M/S pin enables the device to be u sed as a master
and, therefore, the BUSY
line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
output of the master is
). Otherwise, the slave chip
Semaphore Operation
The CY7C024AV/024BV/025AV/026AV and
CY7C0241AV/0251AV/036A V provide eight semaphore latches,
which are separate from the dual port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM
be deasserted for t
The semaphore value is available t
edge of the semaphore write. If the left port was successful
before attempting to read the semaphore.
SOP
SWRD
+ t
(reads a zero), it assumes control of the shared resource.
Otherwise (reads a one), it assumes the right port has con trol
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side succeeds in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE
and RW are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only IO
written to the left port of an available semaphore, a one appears
is used. If a zero is
0
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. T able 3 on page 7 shows sample semaphore
operations.
When reading a semaphore, all 16 and 18 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within t
obtained by one of them. But there is no guarantee which side
of each other, the semaphore is definitely
SPS
controls the semaphore.
or OE must
after the rising
DOE
LOW. The SEM
represents the
0–2
Document #: 38-06052 Rev. *J Page 6 of 19
[+] Feedback