CYPRESS CY7C024, CY7C0241, CY7C025, CY7C0251 User Manual

CY7C024/0241
CY7C025/0251

4K x 16/18 and 8K x 16/18 Dual-Port

Static RAM with SEM, INT, BUSY

Features

• True Dual-Ported memory cells which allow simulta­neous reads of the same memory location

• 4K x 16 organization (CY7C024)

• 4K x 18 organization (CY7C0241)

• 8K x 16 organization (CY7C025)

• 8K x 18 organization (CY7C0251)

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: I

• Fully asynchronous operation

• Automatic power-down

• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device

• On-chip arbitration logic

• Semaphores included to permit software handshaking
between ports

•INT

flag for port-to-port communication

• Separate upper-byte and lower-byte control

• Pin select for Master or Slave

• Available in 84-pin Lead (Pb)-free PLCC, 84-pin PLCC,
100-pin Lead (Pb)-free TQFP, and 100-pin TQFP

= 150 mA (typ.)

CC

Functional Description

The CY7C024/0241 and CY7C025/0251 are low-power
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs.
Various arbitration schemes are included on the CY7C024/
0241 and CY7C025/0251 to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C024/
0241 and CY7C025/0251 can be utilized as standalone
16-/18-bit dual-port static RAMs or multiple devices can be
combined in order to function as a 32-/36-bit or wider master/
slave dual-port static RAM. An M/S
menting 32-/36-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi­processor designs, communications status buffering, and
dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE
Read or Write Enable (R/W
flags are provided on each port (BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt Flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a chip
select (CE

The CY7C024/0241 and CY7C025/0251 are available in
84-pin Lead (Pb)-free PLCCs, 84-pin PLCCs (CY7C024 and
CY7C025 only), 100-pin Lead (Pb)-free Thin Quad Plastic
Flatplack (TQFP) and 100-pin Thin Quad Plastic Flatpack.

) pin.

pin is provided for imple-

), and Output Enable (OE). Two

and INT). BUSY

),

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06035 Rev. *C Revised November 11, 2004

Logic Block Diagram

CY7C024/0241
CY7C025/0251

L

L

L

OE

L

R/W

UB

LB

OE

R

R

R

CE

R

R

(CY7C025/0251) A

Pin Configurations

Notes:

is an output in master mode and an input in slave mode.

1. BUSY
–I/O8 on the CY7C0241/0251.

2. I/O

0

–I/O17 on the CY7C0241/0251.

3. I/O

9

on the CY7C025/0251.

4. A

12L

on the CY7C025/0251.

5. A

12R

[3]

I/O8L–I/O

15L

[2]

I/O0L–I/O

7L

[1] [1]

BUSY

L

12L

A

11L

A

0L

R/W

L

SEM

INT

L

L

7L6L5L4L3L

I/O

I/O

I/O

ADDRESS
DECODER

I/O

CONTROL

MEMORY

ARRAY

CE

L

OE

L

UB

L

LB

L

2L

I/O

I/O

I/O

GND

INTERRUPT
SEMAPHORE
ARBITRATION

M/S

84-Pin PLCC

Top View

L

0L

1L

CC

V

OE

I/O

I/O

R/W

L

1234567891011

I/O

12

8L

I/O

13

9L

14

I/O

10L

15

I/O

11L

16

I/O

12L

17

I/O

13L

18

GND

19

I/O

14L

20

I/O

V

GND

I/O
I/O
I/O

V
I/O
I/O
I/O
I/O
I/O
I/O

15L

CC

21

CC

22
23

0R

24

1R

25

2R

26
27

3R

28

4R

29

5R

6R

30
31

7R

32

8R

9R

10R

I/O

I/O

14R

11R

12R

13R

I/O

I/O

I/O

I/O

GND

15R

I/O

CY7C024/5

42414039383736353433

R

R

OE

R/W

GND

R

CE

SEM

I/O

CONTROL

ADDRESS
DECODER

CE

R

OE

R

UB

R

LB

R

L

L

L

[4]

L

CE

SEM

UB

10L

11L

AAA

9L

75767778798081828384

74
73
72
71
70
69
68
67

NC

LB

66
65
64
63
62
61
60
59

58
57
56
55
54

46454443

47

R

R

R

[5]

LB

UB

A

NC

535251504948

7R

9R

8R

10R

11R

A

A

A

A

[3]

–

I/O8RI/O

15R

[2]

–

I/O

I/O

0R

7R

BUSY

R

(CY7C025/0251)

A

12R

A

11R

A

0R

R/W

R

SEM

R

INT

R

8L

A

A

7L

A

6L

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

BUSY

L

GND
M/S
BUSY

R

INT

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

Document #: 38-06035 Rev. *C Page 2 of 21

Pin Configurations (continued)

I/O9LI/O8LI/O7LI/O6LI/O5LI/O4LI/O3LI/O

2L

GND

I/O1LI/O

100-Pin TQFP

Top View

L

L

L

0L

CC

SEM

OE

V

R/W

CE

CY7C024/0241
CY7C025/0251

[4]

L

L

UBLLB

NC

11LA10L

A

A9LA8LA7LA

6L

I/O
I/O

I/O
I/O

I/O
I/O

I/O
I/O
I/O

I/O
I/O
I/O
I/O

NC
NC
NC
NC

10L

11L
12L

13L

GND

14L

15L

V

GND

V

NC
NC
NC
NC

100 99 9798 96

1
2
3
4
5
6
7
8

9
10
11

CC

0R

1R

2R

CC

3R

4R

5R

6R

12
13
14
15
16
17
18
19
20
21
22
23
24
25

26

27 28 3029 31 32 3534 36 37 3833

I/O7RI/O8RI/O

10L

I/O9LI/O7LI/O6LI/O5LI/O4LI/O3LI/O

I/O

95 94

9R

10R

11R

12R

13R

I/O

I/O

I/O

I/O

2L

9091

14R

15R

GND

I/O

I/O

100-Pin TQFP

GND

I/O1LI/O

89 88 8687 8593 92 84

CY7C024/5

4039

R

R

RCERUBRLBR

Œ

GND

R/W

SEM

Top View

L

L

L

0L

CC

OE

SEM

V

R/W

83 82 81 80 79 78 7 7 76

4241

43 44 45 46 47 48 49 50

[5]

11RA10R

A9RA8RA7RA6RA

A

NC

[4]

L

L

11LA10L

NC

CE

UBLLB

A

A9LA8LA7LA

75
74
73
72
71
70

69
68
67
66
65
64
63

62
61
60
59
58
57
56
55
54
53
52
51

5R

6L

NC
NC
NC
NC
A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT
BUSY
GND
M/S
BUSY
INT

A

0R

A

1R

A

2R

A

3R

A

4R

NC
NC
NC
NC

L

L

R

R

I/O

I/O
I/O
I/O

I/O
I/O

I/O
I/O

I/O

GND

V

GND
I/O
I/O
I/O

V
I/O
I/O
I/O
I/O

I/O

NC
NC

17L

11L

12L
13L

14L

15L

16L

17R

NC
NC

100 99 9798 96

95 94

1
2

8L

3
4
5
6
7
8
9
10
11

CC

0R

1R

2R

CC

3R

4R

5R

6R
8R

12
13
14
15
16
17
18
19
20
21
22
23

24
25

26

27 28 3029 31 32 3534 36 37 3833

7R

I/O

I/O

9R

10R

11R

12R

13R

I/O

14R

I/O

I/O

I/O

I/O

15R

GND

I/O

89 88 8687 8593 92 84

9091

CY7C0241/0251

39

R

R

16R

OE

GND

R/W

I/O

83 82 81 80 79 78 7 7 76

4241

40

43 44 45 46 47 48

RCERUBRLBR

SEM

[

NC

11RA10R

A

49 50

A9RA8RA7RA6RA

75
74
73
72
71
70

69
68
67
66
65
64
63

62
61

60
59
58
57
56
55
54
53

52
51

5R

NC
NC
NC
NC
A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT
BUSY
GND
M/S
BUSY
INT
A

0R

A

1R

A

2R

A

3R

A

4R

NC
NC
NC
NC

L

L

R

R

Document #: 38-06035 Rev. *C Page 3 of 21

CY7C024/0241
CY7C025/0251

Pin Definitions

Left Port Right Port Description

CE

L

R/W

L

OE

L

A

0L–A11/ 12L

I/O

–I/O

0L

15/17L

SEM

SEM

L

UB

L

LB

L

INT

L

BUSY

L

M/S

V

CC

GND Ground

Selection Guide

Maximum Access Time (ns) 15 25 35 55

Typical Operating Current (mA) 190 170 160 150

Typical Standby Current for I

CE

R

R/W

R

OE

R

A0R–A

11/ 12R

I/O0R–I/O

R

UB

R

LB

R

INT

R

BUSY

R

15/17R

Chip Enable

Read/Write Enable

Output Enable

Address

Data Bus Input/Output

Semaphore Enable

Upper Byte Select

Lower Byte Select

Interrupt Flag

Busy Flag

Master or Slave Select

Power

7C024/0241–15
7C025/0251–15

(mA) 50403020

SB1

7C024/0241–25
7C025/0251–25

7C024/0241–35
7C025/0251–35

7C024/0241–55
7C025/0251–55

Architecture

The CY7C024/0241 and CY7C025/0251 consist of an array of
4K words of 16/18 bits each and 8K words of 16/18 bits each
of dual-port RAM cells, I/O and address lines, and control
signals (CE

, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY
provided on each port. Two interrupt (INT

) pins can be utilized

for port-to-port communication. Two semaphore (SEM

pin is

) control
pins are used for allocating shared resources. With the M/S
pin, the CY7C024/0241 and CY7C025/0251 can function as a
master (BUSY

pins are outputs) or as a slave (BUSY pins are
inputs). The CY7C024/0241 and CY7C025/0251 have an
automatic power-down feature controlled by CE
provided with its own output enable control (OE

. Each port is

), which allows

data to be read from the device.

Functional Description

Write Operation

Data must be set up for a duration of t
of R/W

in order to guarantee a valid write. A write operation is

controlled by either the R/W

pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform).
Required inputs for non-contention operations are summa­rized in Ta b l e 1.

If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t

after the data is presented on the other port.

DDD

before the rising edge

SD

Read Operation

When reading the device, the user must assert both the OE
and CE pins. Data will be available t
OE

is asserted. If the user of the CY7C024/0241 or

after CE or t

ACE

DOE

after

CY7C025/0251 wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.

Interrupts

The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024/0241, 1FFF for the CY7C025/0251) is the mailbox
for the right port and the second-highest memory location
(FFE for the CY7C024/0241, 1FFE for the CY7C025/0251) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The
interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.

Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the BUSY

signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active BUSY

to a port prevents that port from reading

its own mailbox and thus resetting the interrupt to it.

If your application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.

The operation of the interrupts and their interaction with Busy
are summarized in Table 2.

Document #: 38-06035 Rev. *C Page 4 of 21

CY7C024/0241
CY7C025/0251

Busy

The CY7C024/0241 and CY7C025/0251 provide on-chip
arbitration to resolve simultaneous memory location access
(contention). If both ports’ CE
match occurs within t
determine which port has access. If t
will definitely gain permission to the location, but which one is
not predictable. BUSY will be asserted t
match or t

after CE is taken LOW.

BLC

s are asserted and an address

of each other, the busy logic will

PS

is violated, one port

PS

after an address

BLA

Master/Slave

A M/S

pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY
Otherwise, the slave chip may begin a write cycle during a

input has settled (t

BLC

or t

BLA

contention situation.When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY
is an output. BUSY

can then be used to send the arbitration

line

outcome to a slave.

Semaphore Operation

The CY7C024/0241 and CY7C025/0251 provide eight
semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports.The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch
by writing a zero to a semaphore location. The left port then
verifies its success in setting the latch by reading it. After
writing to the semaphore, SEM

or OE must be deasserted for
tSOP before attempting to read the semaphore. The
semaphore value will be available t

SWRD

+ t

DOE

after the rising

Table 1. Non-Contending Read/Write

edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the
left side will succeed in gaining control of the semaphore. If the
left side no longer requires the semaphore, a one is written to
cancel its request.

Semaphores are accessed by asserting SEM

LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O
written to the left port of an available semaphore, a one will

).

appear at the same semaphore address on the right port. That

is used. If a zero is

0

semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.

When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to
access the semaphore within t
semaphore will definitely be obtained by one side or the other,

of each other, the

SPS

but there is no guarantee which side will control the
semaphore.

Inputs Outputs

R/W OE UB LB SEM I/O0–I/O

[2]

7

I/O8–I/O

[3]

15

OperationCE

H X X X X H High Z High Z Deselected: Power-Down

X X X H H H High Z High Z Deselected: Power-Down

L L X L H H High Z Data In Write to Upper Byte Only

L L X H L H Data In High Z Write to Lower Byte Only

L L X L L H Data In Data In Write to Both Bytes

L H L L H H High Z Data Out Read Upper Byte Only

L H L H L H Data Out High Z Read Lower Byte Only

L H L L L H Data Out Data Out Read Both Bytes

X X H X X X High Z High Z Outputs Disabled

H H L X X L Data Out Data Out Read Data in Semaphore Flag

X H L H H L Data Out Data Out Read Data in Semaphore Flag

H X X X L Data In Data In Write D

X X H H L Data In Data In Write D

into Semaphore Flag

IN0

into Semaphore Flag

IN0

L X X L X L Not Allowed

L X X X L L Not Allowed

Document #: 38-06035 Rev. *C Page 5 of 21

CY7C024/0241
CY7C025/0251

Table 2. Interrupt Operation Example (Assumes BUSYL=BUSYR=HIGH)

[6]

Left Port Right Port

Function

Set Right INTR Flag L L X (1)FFF X X X X X L

Reset Right INTR Flag X X X X X X L L (1)FFF H

Set Left INTL Flag X X X X L

Reset Left INT

Flag X L L (1)FFE H

L

R/WLCELOELA

0L–11L

INTLR/WRCEROERA

[7]

LLX(1)FFEX

[8]

XXX X X

0R–11R

INT

[8]

[7]

Table 3. Semaphore Operation Example

Function

0

–I/O

Left

15/17

I/O0–I/O

15/17

Right Status

I/O

No action 1 1 Semaphore-free

Left port writes 0 to semaphore 0 1 Left Port has semaphore token

Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore.

Left port writes 1 to semaphore 1 0 Right port obtains semaphore token

Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore

Right port writes 1 to semaphore 0 1 Left port obtains semaphore token

Left port writes 1 to semaphore 1 1 Semaphore-free

Right port writes 0 to semaphore 1 0 Right port has semaphore token

Right port writes 1 to semaphore 1 1 Semaphore-free

Left port writes 0 to semaphore 0 1 Left port has semaphore token

Left port writes 1 to semaphore 1 1 Semaphore-free

Notes:

6. A

7. If BUSY

8. If BUSY

and A

0L–12L

=L, then no change.

R

=L, then no change.

L

, 1FFF/1FFE for the CY7C025.

0R–12R

R

Document #: 38-06035 Rev. *C Page 6 of 21

CY7C024/0241
CY7C025/0251

Maximum Ratings

[9]

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential............... –0.3V to +7.0V

DC Voltage Applied to Outputs

in High-Z State ............................................... –0.5V to +7.0V

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

V

V

V

V

I

I

I

I

I

I

I

OH

OL

IH

IL

IX

OZ

CC

SB1

SB2

SB3

SB4

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

Input HIGH Voltage 2.2 2.2 V

Input LOW Voltage –0.7 0.8 –0.7 0.8 V

Input Leakage Current GND ≤ VI ≤ V

CC

Output Leakage Current Output Disabled,

GND ≤ V

Operating Current VCC = Max., I

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS
Levels)

Standby Current
(Both Ports CMOS
Levels)

CEL and CER ≥ VIH,
f = f

CEL or CER ≥ VIH,
f = f

Both Ports CE and CER ≥
V

CC

or V

One Port CE
CE

R

V

IN

Active Port Outputs, f = f

≤ V

O

CC

= 0 mA,

OUT

[11]

MAX

[11]

MAX

– 0.2V, VIN ≥ VCC – 0.2V

≤ 0.2V, f = 0

IN

≥ VCC – 0.2V,

[11]

or

L

≥ VCC – 0.2V or VIN ≤ 0.2V,

MAX

DC Input Voltage

[10]

........................................–0.5V to +7.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

7C024/0241–15
7C025/0251–15

7C024/0241–25
7C025/0251–25

–10 +10 –10 +10 µA

–10 +10 –10 +10 µA

Com’l 190 300 170 250 mA

Ind 200 320 170 290

Com’l 50 70 40 60 mA

Ind 50 70 75

Com’l 120 180 100 150 mA

Ind 120 180 100 170

Com’l 3 15 3 15 mA

Ind 3 15 3 15

Com’l 110 160 90 130 mA

Ind 110 160 90 150

[11]

CC

UnitMin. Typ. Max. Min. Typ. Max.

Electrical Characteristics Over the Operating Range

7C024/0241–35
7C025/0251–35

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

Notes:

9. The voltage on any input or sI/O pin cannot exceed the power pin during power-up

10. Pulse width < 20 ns.

11. f

MAX

standby I

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

Input HIGH Voltage 2.2 2.2 V

Input LOW Voltage –0.7 0.8 –0.7 0.8 V

Input Leakage Current GND ≤ VI ≤ V

Output Leakage Current Output Disabled, GND ≤ VO ≤ V

= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level

.

SB3

CC

CC

–10 +10 –10 +10 µA

–10 +10 –10 +10 µA

Document #: 38-06035 Rev. *C Page 7 of 21

7C024/0241–55
7C025/0251–55

UnitMin. Typ. Max. Min. Typ. Max.

Electrical Characteristics Over the Operating Range (continued)

Parameter Description Test Conditions

I

I

I

I

I

CC

SB1

SB2

SB3

SB4

Operating Current VCC = Max., I

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS
Levels)

Standby Current
(Both Ports CMOS
Levels)

CEL and CER ≥ VIH,
f = f

CEL or CER ≥ VIH,
f = f

MAX

MAX

[11]

[11]

Both Ports CE and CER ≥
V

– 0.2V, VIN ≥ VCC – 0.2V

CC

≤ 0.2V, f = 0

or V

IN

One Port CE
CE

≥ VCC – 0.2V,

R

V

≥ VCC – 0.2V or VIN ≤ 0.2V,

IN

Active Port Outputs, f = f

L

OUT

or

= 0 mA,

[11]

MAX

[11]

CY7C024/0241
CY7C025/0251

7C024/0241–35
7C025/0251–35

Com’l 160 230 150 230 mA

Ind 160 260 150 260

Com’l 30 50 20 50 mA

Ind 30 65 20 65

Com’l 85 135 75 135 mA

Ind 85 150 75 150

Com’l 3 15 3 15 mA

Ind 3 15 3 15

Com’l 80 120 70 120 mA

Ind 80 135 70 135

7C024/0241–55
7C025/0251–55

UnitMin. Typ. Max. Min. Typ. Max.

Capacitance

[12]

Parameter Description Test Conditions Max. Unit

C

C

IN

OUT

Input Capacitance TA = 25×C, f = 1 MHz,

Output Capacitance 10 pF

AC Test Loads and Waveforms

5V

R1 = 893Ω

OUTPUT

C= 30

pF

(a) Normal Load (Load 1)

OUTPUT

Load (Load 2)

R2 = 347Ω

C = 30 pF

V

= 5.0V

CC

R

OUTPUT

C= 30pF

TH

(b) Thévenin Equivalent (Load 1)

ALL INPUTPULSES

3.0V

GND

≤

10%

3ns

90%

= 250Ω

V

90%

TH

10%

=1.4V

ns

3

≤

10 pF

OUTPUT

C= 5pF

(c) Three-State Delay (Load

5V

R1 = 893Ω

R2 = 347Ω

3)

Note:

12. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-06035 Rev. *C Page 8 of 21

CY7C024/0241
CY7C025/0251

Switching Characteristics Over the Operating Range

7C024/0241–15
7C025/0251–15

Parameter Description

[13]

7C024/0241–25
7C025/0251–25

7C024/0241–35
7C025/0251–35

7C024/0241–55
7C025/0251–55

UnitMin. Max. Min. Max. Min. Max. Min. Max.

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

t

ABE

[14]

[15, 16, 17]

[15, 16, 17]

[15, 16, 17]

[15, 16, 17]

[17]

[17]

[14]

Read Cycle Time 15 25 35 55 ns

Address to Data Valid 15 25 35 55 ns

Output Hold From Address

33 33ns

Change

CE LOW to Data Valid 15 25 35 55 ns

OE LOW to Data Valid 10 13 20 25 ns

OE Low to Low Z 3 3 3 3 ns

OE HIGH to High Z 10 15 20 25 ns

CE LOW to Low Z 3 3 3 3 ns

CE HIGH to High Z 10 15 20 25 ns

CE LOW to Power-Up 0 0 0 0 ns

CE HIGH to Power-Down 15 25 25 55 ns

Byte Enable Access Time 15 25 35 55 ns

Write Cycle

t

WC

[14]

t

SCE

t

AW

t

HA

[14]

t

SA

t

PWE

t

SD

t

HD

[16, 17]

t

HZWE

[16, 17]

t

LZWE

[18]

t

WDD

[18]

t

DDD

Notes:

13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

OI/IOH

14. To access RAM, CE

15. At any given temperature and voltage condition for any given device, t

16. Test conditions used are Load 3.

17. This parameter is guaranteed but not tested.

18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.

Write Cycle Time 15 25 35 55 ns

CE LOW to Write End 12 20 30 35 ns

Address Set-Up to Write End 12 20 30 35 ns

Address Hold From Write

00 00ns

End

Address Set-up to Write Start 0 0 0 0 ns

Write Pulse Width 12 20 25 35 ns

Data Set-Up to Write End 10 15 15 20 ns

Data Hold From Write End 0 0 0 0 ns

R/W LOW to High Z 10 15 20 25 ns

R/W HIGH to Low Z 0 0 0 0 ns

Write Pulse to Data Delay 30 50 60 70 ns

Write Data Valid to Read

25 35 35 45 ns

Data Valid

and 30-pF load capacitance.

=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

.

SCE

time.

Document #: 38-06035 Rev. *C Page 9 of 21

CY7C024/0241
CY7C025/0251

Switching Characteristics Over the Operating Range (continued)

7C024/0241–15
7C025/0251–15

Parameter Description

Busy Timing

t

BLA

t

BHA

t

BLC

t

BHC

t

PS

t

WB

t

WH

[20]

t

BDD

Interrupt Timing

t

INS

t

INR

[19]

BUSY LOW from Address
Match

BUSY HIGH from Address
Mismatch

BUSY LOW from CE LOW 15 20 20 40 ns

BUSY HIGH from CE HIGH 15 20 20 35 ns

Port Set-up for Priority 5 5 5 5 ns

R/W HIGH after BUSY (Slave) 0 0 0 0 ns

R/W HIGH after BUSY HIGH

13 20 30 40 ns

(Slave)

BUSY HIGH to Data Valid Note 20 Note 20 Note 20 Note 20 ns

[19]

INT Set Time 15 20 25 30 ns

INT Reset Time 15 20 25 30 ns

Semaphore Timing

t

SOP

t

SWRD

t

SPS

t

SAA

SEM Flag Update Pulse (OE
or SEM

)

SEM Flag Write to Read Time 5 10 10 15 ns

SEM Flag Contention
Window

SEM Address Access Time 15 25 35 55 ns

10 12 15 20 ns

5101015ns

Data Retention Mode

The CY7C024/0241 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:

1. Chip enable (CE
within V

2. CE

CC

must be kept between VCC – 0.2V and 70% of VCC

during the power-up and power-down transitions.

3. The RAM can begin operation >t
minimum operating voltage (4.5V).

Notes:

19. Test conditions used are Load 2.

20. t

is a calculated parameter and is the greater of t

BDD

21. CE

= VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.

) must be held HIGH during data retention,

to VCC – 0.2V.

after VCC reaches the

RC

– t

WDD

(actual) or t

PWE

7C024/0241–25
7C025/0251–25

15 20 20 45 ns

15 20 20 40 ns

Timing

V

CC

CE

Parameter Test Conditions

ICC

DR1

– t

(actual).

DDD

SD

[13]

7C024/0241–35
7C025/0251–35

Data Retention Mode

4.5V
V

> 2.0V

CC

V

to VCC– 0.2V

CC

7C024/0241–55
7C025/0251–55

4.5V

[21]

t

RC

V

IH

Max. Unit

@ VCCDR = 2V 1.5 mA

UnitMin. Max. Min. Max. Min. Max. Min. Max.

Document #: 38-06035 Rev. *C Page 10 of 21

Switching Waveforms

Read Cycle No. 1 (Either Port Address Access)

ADDRESS

t

AA

t

OHA

DATA OUT

[22, 23, 24]

CY7C024/0241
CY7C025/0251

t

RC

t

OHA

DATA VALIDPREVIOUS DATA VALID

Read Cycle No. 2 (Either Port CE/OE Access)

CE and

LB

or UB

OE

DATA OUT

t

I

CURRENT

I

CC

SB

Read Cycle No. 3 (Either Port)

ADDRESS

UB or LB

[22, 24, 25, 25, 26]

PU

t

AA

t

LZCE

[22, 25, 26]

t

LZOE

t

LZCE

t

ABE

t

t

ACE

RC

t

DOE

t

HZCE

DATA VALID

t

PD

t

OHA

t

HZOE

t

HZCE

CE

t

LZCE

t

ACE

t

HZCE

DATA OUT

Notes:

is HIGH for read cycles

22. R/W

23. Device is continuously selected CE

24. OE

= VIL.

25. Address valid prior to or coincident with CE

26. To access RAM, CE

= VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.

= VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.

transition LOW.

Document #: 38-06035 Rev. *C Page 11 of 21

Switching Waveforms (continued)

CY7C024/0241
CY7C025/0251

Write Cycle No. 1: R/W Controlled Timing

ADDRESS

OE

[31,32]

CE

t

SA

R/W

DATA OUT

NOTE 34

DATA IN

Write Cycle No. 2: CE Controlled Timing

ADDRESS

[27, 28,29, 30]

t

t

AW

[33]

t

HZWE

[27, 28, 29,35]

t

WC

WC

t

PWE

[30]

[33]

t

HZOE

t

HA

t

LZWE

NOTE 34

t

SD

t

HD

t

AW

[31,32]

CE

t

SA

t

SCE

t

HA

R/W

t

SD

t

HD

DATA IN

Notes:

must be HIGH during all address transitions.

27. R/W

28. A write occurs during the overlap (t

29. t

is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

HA

is LOW during a R/W-controlled write cycle, the write pulse width must be the larger of t

30. If OE
placed on the bus for the required t
the specified t

31. To access RAM, CE

32. To access upper byte, CE
To access lower byte, CE

33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.

34. During this period, the I/O pins are in the output state, and input signals must not be applied.

35. If the CE

.

PWE

= VIL, SEM = VIH.

= VIL, UB = VIL, SEM = VIH.

= VIL, LB = VIL, SEM = VIH.

or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

or t

SCE

SD

) of a LOW CE or SEM and a LOW UB or LB.

PWE

or (t

. If OE is HIGH during an R/W-controlled write cycle, this requirement does not apply and the write pulse can be as short as

PWE

+ tSD) to allow the I/O drivers to turn off and data to be

HZWE

Document #: 38-06035 Rev. *C Page 12 of 21

Switching Waveforms (continued)

Semaphore Read After Write Timing, Either Side

A0–A

SEM

I/O

R/W

2

0

t

SA

VALID ADRESS VALID ADRESS

t

AW

t

SCE

t

SD

DATAINVAL ID

t

PWE

CY7C024/0241
CY7C025/0251

[36]

VAL ID

t

OHA

t

AA

t

t

HA

t

SOP

t

HD

ACE

DATA

OUT

OE

WRITE CYCLE READ CYCLE

Timing Diagram of Semaphore Contention

A0L–A

2L

R/W

L

SEM

L

A0R–A

2R

R/W

R

SEM

R

[37, 38, 39]

MATCH

t

SPS

MATCH

t

SWRD

t

SOP

t

DOE

Notes:

= HIGH for the duration of the above timing (both write and read cycle).

36. CE

= I/O0L = LOW (request semaphore); CER = CEL = HIGH.

37. I/O

0R

38. Semaphores are reset (available to both ports) at cycle start.

is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.

39. If t

SPS

Document #: 38-06035 Rev. *C Page 13 of 21

Switching Waveforms (continued)

CY7C024/0241
CY7C025/0251

Timing Diagram of Read with BUSY (M/S=HIGH)

ADDRESS

ADDRESS

DATA

R/W

DATA IN

BUSY

OUTL

R

R

R

t

PS

L

L

Write Timing with Busy Input (M/S=LOW)

[40]

t

BLA

t

WC

MATCH

MATCH

t

PWE

t

SD

VAL ID

t

WDD

t

DDD

t

HD

t

BHA

t

BDD

VAL ID

Note:

40. CE

R/W

BUSY

= CER = LOW.

L

t

WB

t

PWE

t

WH

Document #: 38-06035 Rev. *C Page 14 of 21

Switching Waveforms (continued)

[41]

Busy Timing Diagram No.1 (CE Arbitration)
CELVal id Fi rst:

[41]

CY7C024/0241
CY7C025/0251

ADDRESS

CE

CE

BUSY

L,R

R

R

L

t

PS

CERVal id Firs t:

ADDRESS

CE

CE

BUSY

L,R

R

t

L

L

PS

Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First

ADDRESS MATCH

t

BLC

ADDRESS MATCH

t

BLC

t

BHC

t

BHC

or t

t

RC

WC

ADDRESS

ADDRESS

BUSY

L

R

R

ADDRESS MATCH

t

PS

t

BLA

ADDRESS MISMATCH

t

BHA

Right Address Valid First:

tRCor t

WC

ADDRESS

ADDRESS

Note:

is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

41. If t

PS

BUSY

R

L

L

ADDRESS MATCH ADDRESS MISMATCH

t

PS

t

BLA

t

BHA

Document #: 38-06035 Rev. *C Page 15 of 21

Switching Waveforms (continued)

Interrupt Timing Diagrams
Left Side Sets INTR:

ADDRESS

CE

R/W

INT

L

L

L

R

Right Side Clears INTR:

ADDRESS

CE

R/W

R

R

R

WRITE FFF (1FFF CY7C025)

[43]

t

INS

t

INR

[43]

t

WC

CY7C024/0241
CY7C025/0251

[42]

t

HA

t

RC

READ FFF

(1FFF CY7C025)

OE

R

INT

R

Right Side Sets INT

ADDRESS

CE

R/W

INT

R

R

R

L

L

Left Side Clears INTL:

ADDRESS

CE

R/W

R

L

L

:

t

WC

WRITE FFE (1FFE CY7C025)

[42]

t

HA

[43]

t

INS

t

RC

READ FFE

(1FFE CY7C025)

[43]

t

INR

OE

L

INT

L

Notes:

42. t

depends on which enable pin (CEL or R/WL) is deasserted first.

HA

or t

43. t

depends on which enable pin (CEL or R/WL) is asserted last.

INS

INR

Document #: 38-06035 Rev. *C Page 16 of 21

CY7C024/0241
CY7C025/0251

Ordering Information (4K x16 Dual-Port SRAM)

Speed

(ns) Ordering Code

15 CY7C024–15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C024-15AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C024–15JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C024-15JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

25 CY7C024–25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C024-25AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C024–25JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C024-25JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

CY7C024–25AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C024-25AXI A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C024–25JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C024-25JXI J83 84-Lead Lead Free Plastic Leaded Chip Carrier

35 CY7C024–35AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C024-35AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C024–35JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C024-35JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

CY7C024–35AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C024-35AXI A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C024–35JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C024-35JXI J83 84-Lead Lead Free Plastic Leaded Chip Carrier

55 CY7C024–55AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C024-55AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C024–55JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C024-55JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

CY7C024–55AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C024-55AXI A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C024–55JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C024-55JXI J83 84-Lead Lead Free Plastic Leaded Chip Carrier

Package

Name Package Type

Operating

Range

Ordering Information (8K x 16 Dual-Port SRAM)

Speed

(ns) Ordering Code

15 CY7C025–15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C025-15AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C025–15JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C025-15JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

CY7C025–15AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C025-15AXI A100 100-Pin Lead Free Thin Quad Flat Pack

Document #: 38-06035 Rev. *C Page 17 of 21

Package

Name Package Type

Operating

Range

CY7C024/0241
CY7C025/0251

Ordering Information (8K x 16 Dual-Port SRAM) (continued)

Speed

(ns) Ordering Code

25 CY7C025–25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C025-25AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C025–25JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C025-25JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

CY7C025–25AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C025-25AXI A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C025–25JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C025-25JXI J83 84-Lead Lead Free Plastic Leaded Chip Carrier

35 CY7C025–35AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C025-35AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C025–35JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C025-35JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

CY7C025–35AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C025-35AXI A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C025–35JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C025-35JXI J83 84-Lead Lead Free Plastic Leaded Chip Carrier

55 CY7C025–55AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C025-55AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C025–55JC J83 84-Lead Plastic Leaded Chip Carrier

CY7C025-55JXC J83 84-Lead Lead Free Plastic Leaded Chip Carrier

CY7C025–55AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C025-55AXI A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C025–55JI J83 84-Lead Plastic Leaded Chip Carrier

CY7C025-55JXI J83 84-Lead Lead Free Plastic Leaded Chip Carrier

Package

Name Package Type

Operating

Range

Ordering Information (4K x 18 Dual-Port SRAM)

Speed

(ns) Ordering Code

15 CY7C0241–15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0241-15AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C0241–15AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C0241-15AXI A100 100-Pin Lead Free Thin Quad Flat Pack

25 CY7C0241–25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0241-25AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C0241–25AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C0241-25AXI A100 100-Pin Lead Free Thin Quad Flat Pack

35 CY7C0241–35AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0241-35AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C0241–35AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C0241-35AXI A100 100-Pin Lead Free Thin Quad Flat Pack

55 CY7C0241–55AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0241-55AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C0241–55AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C0241-55AXI A100 100-Pin Lead Free Thin Quad Flat Pack

Document #: 38-06035 Rev. *C Page 18 of 21

Package

Name Package Type

Operating

Range

CY7C024/0241
CY7C025/0251

8K x 18 Dual-Port SRAM

Speed

(ns) Ordering Code

15 CY7C0251–15AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0251–15AXC A100 100-Pin Lead Free Thin Quad Flat Pack

25 CY7C0251–25AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0251-25AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C0251–25AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C0251–25AXI A100 100-Pin Lead Free Thin Quad Flat Pack

35 CY7C0251–35AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0251–35AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C0251–35AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C0251–35AXI A100 100-Pin Lead Free Thin Quad Flat Pack

55 CY7C0251–55AC A100 100-Pin Thin Quad Flat Pack Commercial

CY7C0251–55AXC A100 100-Pin Lead Free Thin Quad Flat Pack

CY7C0251–55AI A100 100-Pin Thin Quad Flat Pack Industrial

CY7C0251–55AXI A100 100-Pin Lead Free Thin Quad Flat Pack

Package

Name Package Type

Operating

Range

Document #: 38-06035 Rev. *C Page 19 of 21

Package Diagrams

100-Pin Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100

CY7C024/0241
CY7C025/0251

84-Lead Lead Free Plastic Leaded Chip Carrier J83

51-85048-*B

51-85006-*A

All product and company names mentioned in this document are trademarks of their respective holders.

Document #: 38-06035 Rev. *C Page 20 of 21

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress does not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C024/0241
CY7C025/0251

Document History Page

Document Title: CY7C024/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy
Document Number: 38-06035

REV. ECN NO. Issue Date

** 110177 09/29/01 SZV Change from Spec number: 38-00255 to 38-06035

*A 122286 12/27/02 RBI Power-up requirements added to Maximum Ratings Information

*B 236754 See ECN YDT Removed cross information from features section

*C 279132 See ECN RUY Added Lead (Pb)-Free packaging information

Orig. of
Change Description of Change

Document #: 38-06035 Rev. *C Page 21 of 21