CYPRESS CY7B993V, CY7B994V User Manual

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Features

RoboClock

CY7B993V
CY7B994V

High-speed Multi-phase PLL Clock Buffe

Functional Description



• 500-ps max. Total Timing Budget™ (TTB™) window

• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)
input/output operation

• Matched pair output skew < 200 ps

• Zero input-to-output delay

• 18 LVTTL outputs driving 50Ω terminated lines

• 16 outputs at 200 MHz: Commercial temperature

• 6 outputs at 200 MHz: Industrial temperature

• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable
reference inputs

• Phase adjustments in 625-/1300-ps steps up to ± 10.4 ns

• Multiply/divide ratios of 1–6, 8, 10, 12

• Individual output bank disable

• Output high-impedance option for testing purposes

• Fully integrated phase-locked loop (PLL) with lock
indicator

• <50-ps typical cycle-to-cycle jitter

• Single 3.3V ± 10% supply

• 100-pin TQFP package

• 100-lead BGA package

Functional
Block Diagram

Feedback Bank

FBKA+
FBKA–
FBKB+
FBKB–

FBSEL
REFA+
REFA–
REFB+
REFB–

REFSEL

Bank 4

Bank 3

Bank 2

Bank 1

FBF0

FBDS0
FBDS1

FBDIS

4F0

4F1
4DS0
4DS1
DIS4

3F0

3F1
3DS0
3DS1

DIS3

INV3

2F0

2F1
2DS0
2DS1

DIS2

1F0

1F1
1DS0
1DS1

DIS1

Phase
Freq.
Detector

OUTPUT_MODE

3
3
3

3
3
3
3

3
3
3
3

3
3
3

3
3

3
3
3
3

The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the
system integrator with functions necessary to optimize the
timing of high-performance computer and communication
systems.

These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.

Eighteen configurable outputs each drive terminated trans­mission lines with impedances as low as 50Ω while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in five banks. Banks 1 to 4 of four outputs allow
a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625–1300-ps increments up to 10.4 ns.
One of the output banks also includes an independent clock
invert function. The feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12 and limited
phase adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.

Selectable reference input is a fault tolerance feature that
allows smooth change-over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.

LOCK

Filter

FS

Divide and
Phase
Select
Matrix

Divide and
Phase
Select
Matrix

Divide and
Phase
Select
Matrix

Divide and
Phase
Select
Matrix

Divide and
Phase
Select
Matrix

QFA0
QFA1

4QA0
4QA1

4QB0
4QB1

3QA0
3QA1

3QB0
3QB1

2QA0
2QA1

2QB0
2QB1

1QA0
1QA1

1QB0
1QB1

Control Logic
Divide and Phase
Generator

VCO

3

3

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07127 Rev. *F Revised August 10, 2005

RoboClock



Pin Configurations

GND

3F1

4F1

3F0

4F0

4DS1

3DS1

GND

4QB1

VCCN

4QB0

GND

GND

4QA1

VCCN

4QA0

GND

2DS1

1DS1

VCCQ

4DS0

3DS0

2DS0

1DS0

GND

CY7B993V
CY7B994V

100-pin TQFP

LOCK

FBDS1

FBDS0

GND

1QB1

VCCN

GND

1QB0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

3332313029282726

VCCN

1QA1

GND

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

GND

GND

1QA0

QFA1

QFA0

GND

VCCN

GND

FBKB+

CY7B993/4V

34 35 36 424139 403837 43 44 45 5048 494746

FBKB–

FBSEL

FBKA–

FBKA+

VCCQ

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VCCQ

REFA+

REFA –

REFSEL

REFB–

REFB+

2F0

FS

GND

2QA0

VCCN

2QA1

GND

GND

2QB0

VCCN

2QB1

GND

FBF0

1F0

GND

VCCQ

FBDIS

DIS4

DIS3

VCCQ

VCCQ

2F1

GND

GND

GND

DIS1

DIS2

GND

3QA0

GND

GND

3QA1

VCCN

3QB0

GND

3QB1

VCCN

VCCQ

GND

INV3

OUTPUT_MODE

VCCQ

GND

1F1

Document #: 38-07127 Rev. *F Page 2 of 15

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

Pin Configurations (continued)

12345678910

1QB1 1QB0 1QA1 1QA0 QFA0 QFA1 FBKB+ VCCQ FBKA– FBKA+

A

VCCN VCCN VCCN VCCN VCCN VCCN VCCQ FBKB– FBSEL REFA+

B

GND GND GND GND GND GND VCCQ GND GND REFA–

C

LOCK

D

4QB1 VCCN

E

4QB0 VCCN

F

4F0

(3_level)

3F1

(3_level)

4DS1

(3_level)

3DS1

(3_level)

100-lead BGA

GND

GND

GND GND GND GND

FBDS1

(3_level)

(3_level)

3F0

FBDS0

(3_level)

4F1

(3_level)

2F0

(3_level)

GND

VCCQ REFSEL REFB–

FS

(3_level)

FBF0

(3_level)

VCCN REFB+

VCCN 2QA0

CY7B993V
CY7B994V

1F0

(3_level)

FBDIS 2QB0

DIS3 2QB1

2QA1

G

H

J

K

Pin Definitions

4QA1

4QA0

4DS0

(3_level)

2F1

(3_level)

[1]

2DS1

(3_level)

1DS1

(3_level)

3DS0

(3_level)

1F1

(3_level)

VCCQ GND GND GND GND VCCQ

1DS0

(3_level)

2DS0

(3_level)

DIS2 VCCN 3QA0 3QA1 GND 3QB0 3QB1 DIS4

VCCQ GND GND VCCQ

DIS1 VCCN VCCN GND

OUTPUT

MODE

(3_level)

INV3

(3_level)

Pin Name I/O Pin Type Pin Description

FBSEL Input LVTTL Feedback Input Select: When LOW, FBKA inputs are selected. When HIGH, the FBKB

inputs are selected. This input has an internal pull-down.

FBKA+, FBKA–
FBKB+, FBKB–

Input LVTTL/

LVDI FF

Feedback Inputs: One pair of inputs selected by the FBSEL is used to feedback the clock
output xQn to the phase detector. The PLL will operate such that the rising edges of the
reference and feedback signals are aligned in both phase and frequency. These inputs
can operate as differential PECL or single-ended TTL inputs. When operating as a
single-ended LVTTL input, the complementary input must be left open.

REFA+, REFA–
REFB+, REFB–

Input LVTTL/

LVDI FF

Reference Inputs: These inputs can operate as differential PECL or single-ended TTL
reference inputs to the PLL. When operating as a single-ended LVTTL input, the comple­mentary input must be left open.

REFSEL Input LVTTL Reference Select Input: The REFSEL input controls how the reference input is

configured. When LOW, it will use the REFA pair as the reference input. When HIGH, it
will use the REFB pair as the reference input. This input has an internal pull-down.

FS Input 3-level

Input

FBF0 Input 3-level

Input

Note:

1. For all three-state inputs, HIGH indicates a connection to V
circuitry holds an unconnected input to V

Frequency Select: This input must be set according to the nominal frequency (f
Tabl e 1).

NOM

Feedback Output Phase Function Select: This input determines the phase function of
the Feedback bank’s QFA[0:1] outputs (see Tab le 3).

, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination

CC

/2.

CC

) (see

Document #: 38-07127 Rev. *F Page 3 of 15

RoboClock



CY7B993V
CY7B994V

Input

Input

Input

Input

Input

[1]

Feedback Divider Function Select: These inputs determine the function of the QFA0
and QFA1 outputs (see Tab le 4 ).

is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is determined by
OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see Table 5). This input has an
internal pull-down.

Output Phase Function Select: Each pair controls the phase function of the respective
bank of outputs (see Tabl e 3).

Output Divider Function Select: Each pair controls the divider function of the respective
bank of outputs (see Tabl e 4).

the output bank is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is deter­mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see Table 5).
These inputs each have an internal pull-down.

Invert Mode: This input only affects Bank 3. When this input is LOW, each matched output
pair will become complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is
HIGH, all four outputs in the same bank will be inverted. When this input is MID all four
outputs will be non inverting.

reference signal. When LOW, the PLL is attempting to acquire lock.

Output Mode: This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs will disable to high-impedance (HI-Z). When this input is LOW,
the clock outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter
factory test mode.

FB input. These outputs have numerous divide options and three choices of phase adjust­ments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.

mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.

Pin Definitions (continued)

Pin Name I/O Pin Type Pin Description

FBDS[0:1] Input 3-level

FBDIS Input LVTTL Feedback Disable: This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1]

[1:4]F[0:1] Input 3-level

[1:4]DS[0:1] Input 3-level

DIS[1:4] Input LVTTL Output Disable: Each input controls the state of the respective output bank. When HIGH,

INV3 Input 3-level

LOCK Output LVTTL PLL Lock Indicator: When HIGH, this output indicates the internal PLL is locked to the

OUTPUT_MODE Input 3-Level

QFA[0:1] Output LVTTL Clock Feedback Output: This pair of clock outputs is intended to be connected to the

[1:4]Q[A:B][0:1] Output LVTTL Clock Output: These outputs provide numerous divide and phase select functions deter-

VCCN PWR Output Buffer Power: Power supply for each output pair.

VCCQ PWR Internal Power: Power supply for the internal circuitry.

GND PWR Device Ground.

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+, or REFB–) and the FB inputs (FBKA+,

FBKA–, FBKB+, or FBKB–). Correction information is then
generated to control the frequency of the voltage-controlled
oscillator (VCO). These two blocks, along with the VCO, form
a PLL that tracks the incoming REF signal.

The CY7B993V/994V have a flexible REF and FB input
scheme. These inputs allow the use of either differential
LVPECL or single-ended LVTTL inputs. To configure as
single-ended LVTTL inputs, the complementary pin must be
left open (internally pulled to 1.5V). The other input pin can
then be used as an LVTTL input. The REF inputs are also
tolerant to hot insertion.

Document #: 38-07127 Rev. *F Page 4 of 15

The REF inputs can be changed dynamically. When changing
from one reference input to the other of the same frequency,
the PLL is optimized to ensure that the clock output period will
not be less than the calculated system budget (t
(nominal reference clock period) – t
t

(max. period deviation)) while reacquiring the lock.

PDEV

VCO, Control Logic, Divider, and Phase Generator

The VCO accepts analog control inputs from the PLL filter
block. The FS control pin setting determines the nominal
operational frequency range of the divide by one output (f
of the device. f
There are two versions: a low-speed device (CY7B993V)
where f
high-speed device (CY7B994V) that ranges from 24 MHz to
200 MHz. The FS setting for each device is shown in Ta bl e 1.

The f
the CY7B994V, the upper f
200 MHz.

NOM

frequency is seen on “divide-by-one” outputs. For

NOM

is directly related to the VCO frequency.

NOM

ranges from 12 MHz to 100 MHz, and a

range extends from 96 MHz to

NOM

(cycle-to-cycle jitter) –

CCJ

MIN

= t

REF

NOM

)

RoboClock



Table 1. Frequency Range Select

CY7B993V CY7B994V

f

(MHz) f

NOM

Min. Max. Min. Max.

FS

[2]

LOW12262452

MID 24 52 48 100

HIGH 48 100 96 200

Time Unit Definition

Selectable skew is in discrete increments of time unit (t
value of a t
nominal output frequency. The equation to be used to
determine the t

t

= 1/(f

U

is determined by the FS setting and the maximum

U

value is as follows:

U

*N).

NOM

N is a multiplication factor which is determined by the FS
setting. f
in Table 2 .

is nominal frequency of the device. N is defined

NOM

Table 2. N Factor Determination

CY7B993V CY7B994V

f

(MHz) at

FS

N

NOM

which tU =1.0 ns N

LOW 64 15.625 32 31.25

MID 32 31.25 16 62.5

HIGH 16 62.5 8 125

Divide and Phase Select Matrix

The Divide and Phase Select Matrix is comprised of five
independent banks: four banks of clock outputs and one bank
for feedback. Each clock output bank has two pairs of
low-skew, high-fanout output buffers ([1:4]Q[A:B][0:1]), two
phase function select inputs ([1:4]F[0:1]), two divider function
selects ([1:4]DS[0:1]), and one output disable (DIS[1:4]).

The feedback bank has one pair of low-skew, high-fanout
output buffers (QFA[0:1]). One of these outputs may connect
to the selected feedback input (FBK[A:B]±). This feedback
bank also has one phase function select input (FBF0), two
divider function selects FSDS[0:1], and one output disable
(FBDIS).

The phase capabilities that are chosen by the phase function
select pins are shown in Tabl e 3. The divide capabilities for
each bank are shown in Table 4.

Notes:

2. The level to be set on FS is determined by the “nominal” operating frequency (f
the output is operating in the undivided mode. The REF and FB are at f

3. BK1, BK2 denotes following the skew setting of Bank1 and Bank2, respectively.

(MHz)

NOM

). The

U

f

(MHz) at

NOM

which tU =1.0 ns

NOM

when the output connected to FB is undivided.

CY7B993V
CY7B994V

Table 3. Output Skew Select Function

Function

Selects Output Skew Function

[1:4]F0

[1:4]F1

LOW LOW –4t

LOW MID –3t

LOW HIGH –2t

MID LOW –1t

MID MID 0t

MID HIGH +1t

HIGH LOW +2t

HIGH MID +3t

HIGH HIGH +4t

and

FBF0 Bank1 Bank2 Bank3 Bank4

U

U

U

U

U

U

U

U

U

–4t

–3tu –7t

–2t

–1tUBK1

0t

+1tUBK2

+2t

+3t

+4t

–8t

U

–6t

U

0t

U

+6t

U

+7t

U

+8t

U

–8t

U

–7t

U

–6t

U

[3]

BK1

0t

U

[3]

BK2

+6t

U

+7t

U

+8t

U

Table 4. Output Divider Function

Function

Selects Output Divider Function

[1:4]DS1

and

FBDS1

[1:4]DS0

and

FBDS0

Bank1Bank2Bank3Bank

LOW LOW /1 /1 /1 /1 /1

LOW MID /2 /2 /2 /2 /2

LOW HIGH /3 /3 /3 /3 /3

MID LOW /4 /4 /4 /4 /4

MID MID /5 /5 /5 /5 /5

MID HIGH /6 /6 /6 /6 /6

HIGHLOW/8/8/8/8 /8

HIGH MID /10 /10 /10 /10 /10

HIGH HIGH /12 /12 /12 /12 /12

Figure 1 illustrates the timing relationship of programmable
skew outputs. All times are measured with respect to REF with
the output used for feedback programmed with 0t
PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to
another skew position, then the whole t
respect to REF. For example, if the output used for feedback

matrix will shift with

U

is programmed to shift –8tU, then the whole matrix is shifted
forward in time by 8t
of skew will effectively be skewed 16tU with respect to REF.

) of the VCO and Phase Generator. f

NOM

. Thus an output programmed with 8t

U

always appears on an output when

NOM

Feed-

back

Bank

–4t

U

U

U

[3]

U

[3]

U

U

+4t

U

Feed-

back

4

Bank

skew. The

U

NA

NA

NA

0tu

NA

NA

NA

U

U

U

Document #: 38-07127 Rev. *F Page 5 of 15