Cypress CY7B9920, CY7B9910 User Manual
CY7B9910
CY7B9920
Low Skew Clock Buffer
Features
TEST
FB
REF
VOLTAGE
CONTROLLED
OSCILLATOR
FS
Q0
FILTER
PHASE
FREQ
DET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Logic Block Diagram
■ All outputs skew <100 ps typical (250 max.)
■ 15 to 80 MHz output operation
■ Zero input to output delay
■ 50% duty cycle outputs
■ Outputs drive 50Ω terminated lines
■ Low operating current
■ 24-pin SOIC package
■ Jitter:<200 ps peak to peak, <25 ps RMS
Functional Description
The completely integrated PLL enables “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50Ω. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
VCO
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07135 Rev. *B Revised August 07, 2007
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CY7B9910
CY7B9920
Pin Configuration
Q4
Q2
REF
V
CCQ
FS
NC
V
CCQ
V
CCN
Q0
Q1
GND
Q3
V
CCN
GND
TEST
NC
GND
V
CCN
Q7
Q6
GND
Q5
V
CCN
FB
SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
7B9910
7B9920
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicat es a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appear ing at the REF
and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a
frequency multiplication by using external division in the feedback path of value X.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V.
Pin Definitions
Signal Name IO Description
REF I Reference frequency input.This input supplies the frequency and timing against which all functional
variations are measured.
FB I PLL feedback input (typically connected to one of the eight outputs).
[1,2,3]
FS
TEST I Three level select. See TEST MODE.
Q[0..7] O Clock outputs.
V
CCN
V
CCQ
GND PWR Ground.
I Three level frequency range select.
PWR Power supply for output drivers.
PWR Power supply for internal circuitry.
Test Mode
The TEST input is a three level input. In normal system operation, this pin is conn ected to ground, allowing the CY7B9910 and
CY7B9920 to operate as described in Block Di agram Description. For testing purposes, any of the three level inputs can have a
removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input
levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Document Number: 38-07135 Rev. *B Page 2 of 11
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CY7B9910
CY7B9920
Maximum Ratings
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Storage Temperature .................................–65
Ambient Temperature with
Power Applied ............................................–55
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage..................................... .. .....–0.5V to +7.0V
Output Current into Outputs (LOW).............................64 mA
°C to +150°C
°C to +125°C
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Ambient
Temperature V
CC
Document Number: 38-07135 Rev. *B Page 3 of 11
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CY7B9910
CY7B9920
Electrical Characteristics Over the Operating Range
CY7B9910 CY7B9920
Parameter Description Test Conditions Min Max Min Max Unit
V
OH
V
OL
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IH
I
IL
I
IHH
I
IMM
I
ILL
I
OS
I
CCQ
I
CCN
PD Power Dissipation per
Notes
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
5. Te sted one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit
protected.
6. To tal output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
ICCN = [(3.5+.17F) + [((1160 – 2.8 F) /Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C.
7. To tal power dissipation per output p air is approximated by the following expression that includ es device power dissipation plus power dissipa tion due to the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1.See note 3 for variable definition.
Output HIGH Volt age VCC = Min, IOH = –16 mA 2.4 V
VCC = Min, IOH =–40 mA VCC–0.75
Output LOW Voltage VCC = Min, IOL = 46 mA 0.45 V
VCC = Min, IOL = 46 mA 0.45
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
2.0 V
CC
VCC –
1.35
V
CC
–0.5 0.8 –0.5 1.35 V
(REF and FB inputs only)
Three Level Input HIGH
Voltage (Test, FS)
Three Level Input MID
Voltage (Test, FS)
Three Level Input LOW
Voltage (Test, FS)
[4]
[4]
[4]
Input HIGH Leakage Current
Min ≤ VCC ≤ Max VCC – 1V V
Min ≤ VCC ≤ Max VCC/2 –
500 mV
VCC/2 +
500 mV
CC
VCC – 1V V
VCC/2 –
500 mV
VCC/2 +
500 mV
CC
Min ≤ VCC ≤ Max 0.0 1.0 0.0 1.0 V
VCC = Max, VIN = Max 10 10 μA
(REF and FB inputs only)
Input LOW Leakage Current
VCC = Max, VIN = 0.4V –500 –500 μA
(REF and FB inputs only)
Input HIGH Current
(Test, FS)
Input MID Current
VIN = V
CC
200 200 μA
VIN = VCC/2 –50 50 –50 50 μA
(Test, FS)
Input LOW Current
VIN = GND –200 –200 μA
(Test, FS)
Output Short Circuit
[5]
Current
Operating Current Used by
Internal Circuitry
Output Buffer Current per
Output Pair
Output Pair
[6]
[7]
VCC = Max, V
= GND (25
V
= V
CCN
Input
OUT
°C only)
= Max All
CCQ
Selects Open
V
= V
= V
CCQ
CCQ
= Max
= Max
CCN
= 0 mA
I
OUT
Input Selects Open, f
V
CCN
I
= 0 mA
OUT
Input Selects Open, f
–250 N/A mA
Com’l 85 85 mA
Mil/Ind 90 90
14 19 mA
MAX
78 104
MAX
[5]
V
V
V
mW
Document Number: 38-07135 Rev. *B Page 4 of 11
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