Cypress CY7B9911V User Manual

CY7B9911V

3.3V RoboClock+™

High Speed Low Voltage Programmable Skew

Clock Buffer

Features

TEST

FB

REF

VCO AND

TIME UNIT

GENERATOR

FS

SELECT

INPUTS
(THREE

LEVEL)

SKEW

SELECT

MATRIX

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

FILTER

PHASE

FREQ

DET

Functional Description

■ All output pair skew <100 ps typical (250 max)

■ 3.75 to 110 MHz output operation

■ User selectable output functions
❐ Selectable skew to 18 ns
❐ Inverted and non-inverted

❐ Operation at
❐ Operation at 2x and 4x input frequency (input as low as

1

⁄

and

2

1

⁄

input frequency

4

3.75 MHz)

■ Zero input-to-output delay

■ 50% duty cycle outputs

■ LVTTL outputs drive 50Ω terminated lines

■ Operates from a single 3.3V supply

■ Low operating current

■ 32-pin PLCC package

■ Jitter 100 ps (typical)

Logic Block Diagram

The CY7B9911V 3.3V RoboClock+™ High Speed Low
Voltage Programmable Skew Clock Buff er (LVPSCB) offers
user selectable control over system clock functions. These
multiple output clock drivers provide the system integrator with
functions necessary to optimize the timing of high perfor­mance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50Ω.
They deliver minimal and specified output skews and full swing logic
levels (L VTTL).

Each output is hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter­mined by the operating frequency with outputs that can skew
up t o ±6 time units from their nominal “zero” skew position. Th e
completely integrated PLL allows external load and cancels
the transmission line delay effects. When this “zero delay”
capability of the LVPSCB is combined with the selectable
output skew functions, you can create output-to-output delays
of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low frequency clock that are multiplied
by two or four at the clock destination. This facility minimizes
clock distribution difficulty enabling maximum system clock
speed and flexibility.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07408 Rev. *D Revised June 20, 2007

[+] Feedback

CY7B9911V

3.3V RoboClock+™

1234323130

17161514 18 19 20

5
6

7
8
9

10
11

12
13

29
28
27
26
25
24
23
22
21

3F0

FS

V

REF

GND

TEST

2F1

FB

2Q1

2Q0

CCQ

2F0
GND
1F1
1F0
V

CCN

1Q0
1Q1
GND
GND

3Q1

3Q0

CCNVCCN

V

3F1
4F0

4F1

V

CCQ

V

CCN

4Q1

4Q0
GND
GND

PLCC

CY7B9911V

Pin Configuration

Pin Definitions

Signal Name IO Description

REF I Reference frequency input. This input supplies the frequency and timing against which all functional

variations are measured.
FB I PLL feedback input (typically connected to one of the eight outputs).
FS I Three level frequency range select. See Table1.
1F0, 1F1 I Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1 I Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1 I Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1 I Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST I Three level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3.
1Q0, 1Q1 O Output pair 1. See Table 2.
2Q0, 2Q1 O Output pair 2. See Table 2.
3Q0, 3Q1 O Output pair 3. See Table 2.
4Q0, 4Q1 O Output pair 4. See Table 2.
V

CCN

V

CCQ

GND PWR Ground.

Document Number: 38-07408 Rev. *D Page 2 of 14

PWR Power supply for output drivers.
PWR Power supply for internal circuitry.

[+] Feedback

CY7B9911V

3.3V RoboClock+™

Block Diagram Description

t

U

1

f

NOM

N×

----------------------- -

=

Notes

1. For all three-state inputs, HIGH indicates a connection to V

CC

, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination

circuitry holds an unconnected input to V

CC

/2.

2. The level to be set on FS is determined by the “normal” operating frequency (f

NOM

) of the VCO and Time Unit Generator (see). Nominal frequency (f

NOM

) always

appears at 1Q0 and the other outputs when they are op erated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is f

NOM

when the output connected to FB is undivided. The frequency of the REF and FB inp uts is f

NOM

/2 or f

NOM

/4 when the part is configured for a frequency multi plication

using a divided output as the FB input.

3. When the FS pin is selected HIGH, the REF input must not transition upon power up until V

CC

has reached 2.8V.

Phase Frequency Detector and Filter

The Phase Frequency Detector and Filter blocks accept inputs
from the Reference Frequency (REF) input and the Feedback
(FB) input. They generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (t
frequency of the device and the level of the FS pin as shown in

Table 1.

Table 1. Frequency Range Select and t

f

(MHz)

NOM

[2, 3]

FS

Min Max

LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 110 16 62.5

) is determined by the operating

U

Calculation

U

Approximate

Frequency (MHz) At

where N =

Which tU = 1.0 ns

[1]

Skew Select Matrix

The skew select matrix is comprised of four independent
sections. Each section has two low skew, high fanout drivers
(xQ0, xQ1), and two corresponding three level function select
(xF0, xF1) inputs. Table 2 shows the nine possible output
functions for each section as determined by the function select
inputs. All times are measured with respect to the REF input
assuming that the output connected to the FB input has 0t
selected.

Table 2. Programmable Skew Configurations

Function Selects Output Functions

1F1, 2F1,

3F1, 4F1

LOW LOW –4t
LOW MID –3t
LOW HIGH –2t
MID LOW –1t
MID MID 0t
MID HIGH +1t
HIGH LOW +2t
HIGH MID +3t
HIGH HIGH +4t

1F0, 2F0,

3F0, 4F0

1Q0, 1Q1,

2Q0, 2Q1

U
U
U
U

U

U
U
U
U

3Q0, 3Q1 4Q0, 4Q1

Divide by 2 Divide by 2

–6t
–4t
–2t

0t
+2t
+4t
+6t

Divide by 4 Inverted

[1]

U
U
U

U

U
U
U

–6t
–4t
–2t

0t
+2t
+4t
+6t

U
U
U

U

U
U
U

U

Document Number: 38-07408 Rev. *D Page 3 of 14

[+] Feedback

CY7B9911V

3.3V RoboClock+™

Figure 1 shows the typical outputs with FB connected to a zero skew output.

t

0

– 6t

U

t

0

– 5t

U

t

0

– 4t

U

t

0

– 3t

U

t

0

– 2t

U

t

0

– 1t

U

t 0t

0

+1t

U

t 0t 0t 0t 0t

0

+2tU+3tU+4tU+5tU+6t

U

FB Input

REFInput

– 6t

U

– 4t

U

– 3t

U

– 2t

U

– 1t

U

0t

U

+1t

U

+2t

U

+3t

U

+4t

U

+6t

U

DIVIDED

INVERT

LM
LH

(N/A)

ML

(N/A)

MM

(N/A)

MH

(N/A)

HL

HM

LL/HH

HH

3Fx
4Fx

(N/A)

LL

LM

LH

ML
MM
MH

HL
HM

HH

(N/A)
(N/A)
(N/A)

1Fx
2Fx

Note

4. FB connected to an output selected for “zero” skew (that is, xF1 = xF0 = MID).

Figure 1. The Typical Outputs with FB Connected to a Zero Skew Output

[4]

Test Mode

The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B9911V to operate as described in “Block Diagram

Description” on page 3. For testing purposes, any of the three

level inputs can have a removable jumper to ground or b e tied
LOW through a 100W resistor. This enables an external tester to
change the state of these pins.

Document Number: 38-07408 Rev. *D Page 4 of 14

If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly control all outputs. Relative
output-to-output functions are the same as in normal mode.

In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.

[+] Feedback

CY7B9911V

3.3V RoboClock+™

Operational Mode Descriptions

SYSTEM
CLOCK

L1

L2

L3

L4

LENGTH L1 = L2 = L3 = L4

FB
REF

FS
4F0

4F1
3F0

3F1
2F0

2F1
1F0

1F1

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

TEST

Z

0

LOAD

LOAD

LOAD

LOAD

REF

Z

0

Z

0

Z

0

LENGTH L1 = L2

L3 < L2 by 6 inches
L4 > L2 by 6 inches

SYSTEM
CLOCK

L1

L2

L3

L4

FB
REF

FS
4F0

4F1
3F0

3F1
2F0

2F1
1F0

1F1

4Q0
4Q1

3Q0
3Q1

2Q0
2Q1

1Q0
1Q1

TEST

Z

0

LOAD

LOAD

LOAD

LOAD

REF

Z

0

Z

0

Z

0

Figure 2. Zero Skew and Zero Delay Clock Driver

Figure 2 shows the L VPSCB configured as a zero skew clock buf fer . In this mode the CY7B9911V is used as the basis for a low skew

clock distribution tree. When all the function select inputs (xF0, xF1) are left open, each of the outputs are aligned and driv e a
terminated transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency
range is selected with the FS pin. The low skew specification, along with the ability to drive terminated transmission lines (with
impedances as low as 50Ω), enables efficient printed circuit bo ard design.

Figure 3. Programmable Skew Clock Driver

Figure 3 shows a configuration to equalize skew between metal

traces of different lengths. In addition to low skew between
outputs, the LVPSCB is programmed to stagger the timing of its
outputs. Each of the four groups of output pairs is programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4Q0 output is sent
back to FB and configured for zero skew. The other three pairs
of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or

Document Number: 38-07408 Rev. *D Page 5 of 14

retarding the clock signal on shorter traces, all loads receive the
clock pulse at the same time.

In Figure 3 the FB input is connected to an output with 0 ns skew
(xF1, xF0 = MID) selected. The internal PLL synchronizes the FB
and REF inputs and aligns their rising edges to make certain that
all outputs have precise phase alignment.

Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and – tU are de fined relative to output

[+] Feedback