CYPRESS CY7B9911 User Manual

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CY7B9911

RoboClock+

Programmable Skew Clock Buffer (PSCB)

Features

tions. This multiple-out put clock dri ver provide s the system in­tegrator with functions necessary to optimize the timing of

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 100-MHz output operation

• User-selectable output functions
—Selectable skew to 18 ns
—Inverted and non-inverted
—Operation at ½ and ¼ input frequency
—Operation at 2x and 4x in put frequency (input as low

as 3.75 MHz)

• Zero input to output delay

• 50% duty-cycle outputs

• Outputs drive 50Ω terminated lines

• Low operating current

• 32-pin PLCC/LCC package

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Compatible with a Pentium™-based processor

Functional Description

high-performance computer systems. Eight individual TTL
drivers, arranged as four pairs of user-controllable outputs,
can each drive termin ated transmissio n lines with impedan ces
as low as 50Ω while delivering minimal and specified output skews
and full-swing logic levels.

Each output can be h ard wired to one of nine delay o r function
configurations. Delay increments of 0.6 to 1.5 ns are deter­mined by the operating frequency with outputs able to s kew up
to ±6 time units from their nominal “zero” skew position. The com­pletely integrated PLL allows external load a nd transmission line
delay effects to be canceled. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi­plied by two or four at the clock destination. This facility mini­mizes clock d istributi on dif ficul ty while al lowing maximu m sys­tem clock speed and flexibility.

The CY7B991 1 High Speed Programma ble Skew Clock Buffer
(PSCB) offers user-selectable control over system clock func-

Logic Block Diagram Pin Configuration

TEST

PHASE

FB

REF

FREQ

DET

FILTER

VCO AND

TIME UNIT

GENERATOR

3F0

FS

PLCC/LCC

CCQ

V

REF

GND

TEST

2F1

FS

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

SELECT

INPUTS
(THREE

LEVEL)

SKEW

SELECT

MATRIX

7B9911–1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

3F1
4F0

4F1

V

CCQ

V

CCN

4Q1

4Q0
GND
GND

5
6

7
8
9

10
11

12
13

3Q1

1234323130

CY7B9911

17161514 18 19 20

FB

CCNVCCN

3Q0

2Q1

V

2F0

29
28

GND

27

1F1

26

1F0

25

V

CCN

24

1Q0

23

1Q1

22

GND
GND

21

2Q0

7B9911–2

Pentium is a trademark of Intel Corporation.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07209 Rev. ** Revised September 26, 2001

CY7B9911

RoboClock+

Pin Definitions

Signal

Name I/O Description

REF I Reference frequency input. This input supplies the frequency and timing against which all function al

variatio n is measured.
FB I PLL feedback input (typically connected to one of the eight outputs).
FS I Three-level frequency range select. See Table 1.
1F0, 1F1 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2
3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2
4F0, 4F1 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2
TEST I Three-level select. See test mode section under the block diagram descriptions.
1Q0, 1Q1 O Output pair 1. See Table 2.
2Q0, 2Q1 O Output pair 2. See Table 2.
3Q0, 3Q1 O Output pair 3. See Table 2.
4Q0, 4Q1 O Output pair 4. See Table 2.
V

CCN

V

CCQ

GND PWR Ground.

PWR Power supply for output drivers.
PWR Power supply for internal circuitry.

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept inputs from the reference frequency
(REF) input and the fe edbac k (FB) i nput a nd gen erate c orrec­tion information to control the frequency of the Voltage-Con­trolled Oscillator (VCO). These blocks, along with the VCO,
form a Phase-Locked Loop (PLL) that tracks the incoming
REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter
block and generates a frequency that is used by the time unit
generator to create di sc rete time units that are sele cte d i n th e
skew select matrix. The operational range of the VCO is de­termined by the FS control pin. The time unit (t
by the operating frequency of the device and the level of the
FS pin as shown in Table 1.

Table 1. Frequency Range Select and tU Calculation

f

(MHz)

FS

NOM

U

[2, 3]

1

----------------------- -

=

f

NOM

where N =

N×

LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 100 16 62.5

Skew Select Matrix

The skew select ma trix is c om pri se d of fo ur independent sec­tions. Each section has two low-skew, high-fanout drivers
(xQ0, xQ1), and tw o c orre sp ond ing t hree - lev el f unc tio n se lec t

) is determined

U

[1]

Approximate

Frequency (MHz) At

Which tU = 1.0 nsMin. Max.

(xF0, xF1) inputs. Table 2 below shows the nine possible out-
put functions for each section as determined by the function
select inputs. All times are measured with respect to the REF
input assuming that the output connected to the FB input has

selected.

0t

U

Table 2. Programmable Skew Configurations

[1]

Function Selects Output Functions

1F1, 2F1,

3F1, 4F1

LOW LOW –4t
LOW MID –3t
LOW HIGH –2t
MID LOW –1t
MID MID 0t
MID HIGH +1t
HIGH LOW +2t
HIGH MID +3t
HIGH HIGH +4t

Notes:

1. For all three-state inputs, HIGH indicates a connection to V

2. The level to be set on FS is determined by the “normal” operating fre-

3. When the FS pin is selected HIGH, the REF input must not transition

1F0, 2F0,

3F0, 4F0

indicates a connection to GND, and MID indicates an open connection.
Internal termination circuitry holds an unconnected input to V

quency (f
Diagram). Nominal frequency (f
other outputs when they are operated in their undivided modes (see
Table 2). The frequency appearing at the REF and FB inputs will be f
when the output connected to FB is undivided. The frequency of the REF
and FB inputs will be f
frequency multiplication by using a divided output as the FB input.

upon power-up until V

) of the VCO and Time Unit Generator (see Logic Block

NOM

1Q0, 1Q1,

2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1

Divide by 2 Divide by 2

U
U
U
U

U

U
U
U
U

NOM

/2 or f

NOM

CC

NOM

has reached 4.3V.

–6t

U

–4t

U

–2t

U

0t

U

+2t

U

+4t

U

+6t

U

Divide by 4 Inverted

) always appears at 1Q0 and the

/4 when the part is configured for a

–6t
–4t
–2t

+2t
+4t
+6t

CC

CC

U
U
U

0t

U

U
U
U

, LOW

/2.

NOM

Document #: 38-07209 Rev. ** Page 2 of 12

1Fx
2Fx

(N/A)

3Fx
4Fx

LM

FB Input

REF Input

– 6t

CY7B9911

RoboClock+

U

U

U

U

U

U

– 6t

– 5t

– 4t

– 3t

– 2t

0

0

0

t

t

U

0

t

t

– 1t

0

0

t

t

t 0t

U

+1t

+2tU+3tU+4tU+5tU+6t

0

t 0t 0t 0t 0t

U

0

LL
LM

LH

ML
MM
MH

HL
HM
HH

(N/A)
(N/A)
(N/A)

LH

(N/A)

ML

(N/A)

MM

(N/A)

MH

(N/A)

HL

HM

LL/HH

HH

– 4t
– 3t

– 2t
– 1t

0t
+1t
+2t
+3t
+4t

+6t

DIVIDED

INVERT

U

U

U

U

U

U

U

U

U
U

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

Test Mode

The TEST input is a three-level input. In normal system oper­ation, this pin i s con nec ted to ground, allowing the C Y7B9 911
to operate as explained briefly above (for testing purposes,
any of the three-level inputs can have a removable jumper to
ground, or be tied LOW through a 10 0Ω resistor. This will allow
an external tester to change the state of these pins.)

If the TEST input is forced to its MID or HI GH sta te, the dev ice
will operate with its internal phase locked loop disconnected,
and input levels s upplied to REF w ill directly control a ll outputs.
Relative output to output functions are the same as in normal
mode.

In contrast with normal operatio n (TEST tied LOW). All outputs
will function base d only on the conn ection of their own f unction
select inputs (xF0 and xF1) and the waveform characteristics
of the REF input.

7B9911–3

[4]

Maximum Ratings

(Above which the usefu l l ife may be impaired. For us er g uid e­lines, not tested.)

Storage Temperature .................................–65

°C to +150°C

Ambient Temper atu re with

Power Applied............................................–55

°C to +125°C

Supply Voltage to Ground Potential ...............–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

Output Current into Outputs (LOW).............................64 mA

Static Discharge Voltage...........................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Range

Temperature V

CC

Commercial 0°C to +70°C 5V ± 10%

Ambient

Note:

4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 =
MID).

Document #: 38-07209 Rev. ** Page 3 of 12

CY7B9911

RoboClock+

Electrical Characteristics Ov er the Op erat ing Range

CY7B9911

Parameter Description Test Conditions Min. Max. Unit

V

OH

V

OL

V

IH

V

IL

V

IHH

V

IMM

V

ILL

I

IH

I

IL

I

IHH

I

IMM

I

ILL

I

OS

I

CCQ

I

CCN

PD Power Dissipation per

Notes:

5. These inputs are normally wired to V
unconnected inputs at V
before all datasheet limits are achieved.

6. CY7B9911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.

7. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B9911: I
Where

8. T otal power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power di s si pa t ion d u e to
the load circuit:
CY7B9911: PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
See note 7 for variable definition.

Output HIGH Voltage VCC = Min., IOH = –16 mA 2.4 V

VCC = Min., IOH =–40 mA

Output LOW Voltage VCC = Min., IOL = 46 mA 0.45 V

VCC = Min., IOL = 46 mA

Input HIGH Voltage
(REF and FB inputs only)

Input LOW Voltage

2.0 V

CC

–0.5 0.8 V

(REF and FB inputs only)
Three-Level Input HIGH

Voltage (Test, FS, xFn)
Three-Level Input MID

Voltage (Test, FS, xFn)
Three-Level Input LOW

Voltage (Test, FS, xFn)

[5]

[5]

[5]

Input HIGH Leakage Current (REF an d

Min. ≤ VCC ≤ Max. VCC – 0.85 V

CC

Min. ≤ VCC ≤ Max. VCC/2 – 500 mV VCC/2 + 500 mV V

Min. ≤ VCC ≤ Max. 0.0 0.85 V

VCC = Max., VIN = Max. 10 µA

FB inputs only)
Input LOW Leakage Cur rent (REF and

VCC = Max., VIN = 0.4V –500 µA

FB inputs only)
Input HIGH Current

(Test, FS, xFn)
Input MID Current

VIN = V

CC

200 µA

VIN = VCC/2 –50 50 µA

(Test, FS, xFn)
Input LOW Current

VIN = GND –200 µA

(Test, FS, xFn)
Output Short Circuit

[6]

Current
Operating Current Used by

Internal Circuitry

VCC = Max., V

= V

°C only)

CCQ

= GND (25
V

CCN

Max., All Input

OUT

=

–250 mA

Com’l 85 mA

Selects Open

Output Buffer Current per
Output Pair

Output Pair

= [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1

CCN

F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2

∗ C

FC = F

[7]

[8]

, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold

CC

/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t

CC

V

= V

= V

CCQ

CCQ

= Max.,

= Max.,

CCN

= 0 mA

I

OUT

Input Selects Open, f
V

CCN

= 0 mA

I

OUT

Input Selects Open, f

14 mA

MAX

78 mW

MAX

LOCK

V

V

time

Document #: 38-07209 Rev. ** Page 4 of 12