Cypress CY7B991, CY7B992 User Manual

CY7B991
CY7B992

Programmable Skew Clock Buffer

Features

TEST

FB

REF

VCO AND

TIME UNIT

GENERATOR

FS

SELECT

INPUTS
(THREE

LEVEL)

SKEW

SELECT

MATRIX

4F0
4F1

3F0
3F1

2F0
2F1

1F0
1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

FILTER

PHASE

FREQ

DET

Functional Description

■ All output pair skew <100 ps typical (250 maximum)

■ 3.75 to 80 MHz output operation

■ User selectable output functions
❐ Selectable skew to 18 ns

❐ Inverted and non-inverted
❐ Operation at 1⁄2 and 1⁄4 input frequency
❐ Operation at 2x and 4x input frequency (input as low as 3.75

MHz)

■ Zero input to output delay

■ 50% duty cycle outputs

■ Outputs drive 50Ω terminated lines

■ Low operating current

■ 32-pin PLCC/LCC package

■ Jitter < 200 ps peak-to-peak (< 25 ps RMS)

Logic Block Diagram

The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high perfor­mance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50Ω.
They can deliver minimal and specified output skews and full
swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and trans­mission line delay effects. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07138 Rev. *B Revised June 22, 2007

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CY7B991
CY7B992

Pin Configuration

1234323130

17161514 18 19 20

5

6

7

8

9

10

11

12

13

29

28

27

26

25

24

23

22

21

3F0

FS

V

REF

GND

TEST

2F1

FB

2Q1

2Q0

CCQ

2F0

GND

1F1

1F0

V

CCN

1Q0

1Q1

GND

GND

3Q1

3Q0

CCN

V

CCN

V

3F1

4F0

4F1

V

CCQ

V

CCN

4Q1

4Q0

GND

GND

PLCC/LCC

CY7B991
CY7B992

Pin Definitions

Signal Name IO Description

REF I Reference frequency input. This input supplies the frequency and timing against which all functional

variations are measured.
FB I PLL feedback input (typically connected to one of the eight outputs).
FS I Three level frequency range select. See Table 1.
1F0, 1F1 I Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1 I Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1 I Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1 I Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST I Three level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3.
1Q0, 1Q1 O Output pair 1. See Table 2.
2Q0, 2Q1 O Output pair 2. See Table 2.
3Q0, 3Q1 O Output pair 3. See Table 2.
4Q0, 4Q1 O Output pair 4. See Table 2.
V

CCN

V

CCQ

GND PWR Ground.

PWR Power supply for output drivers.
PWR Power supply for internal circuitry.

Document Number: 38-07138 Rev. *B Page 2 of 19

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CY7B992

Block Diagram Description

t

U

1

f

NOM

N×

----------------------- -

=

Notes

1. For all tri-state inputs, HIGH indicates a co nnection to VCC, LOW indicates a connection to GND, and MI D indicates an open connection. I nternal termination circuitr y
holds an unconnected input to VCC/2.

2. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and T ime Unit Generat or (see Logic Block Diagram ). Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.

3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3V.

Phase Frequency Detector and Filter

The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (t
frequency of the device and the level of the FS pin as shown in

Table 1.

Table 1. Frequency Range Select and tU Calculation

f

(MHz)

NOM

[2, 3]

FS

Min Max

LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH 40 80 16 62.5

) is determined by the operating

U

Approximate

Frequency (MHz) At

where N =

Which tU = 1.0 ns

[1]

Skew Select Matrix

The skew select matrix contains four independent sections. Each
section has two low skew, high fanout drivers (xQ0, xQ1), and
two corresponding three level function select (xF0, xF1) inpu ts.

Table 2 shows the nine possible output functions for each section

as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0t

Table 2. Programmable Skew Configurations

Function Selects Output Functions

1F1, 2F1,

3F1, 4F1

1F0, 2F0,

3F0, 4F0

1Q0, 1Q1,

2Q0, 2Q1

LOW LOW –4t
LOW MID –3t
LOW HIGH –2t
MID LOW –1t
MID MID 0t
MID HIGH +1t
HIGH LOW +2t
HIGH MID +3t
HIGH HIGH +4t

selected.

U

3Q0, 3Q1 4Q0, 4Q1

Divide by 2 Divide by 2

U
U
U
U

U

U
U
U
U

–6t

U

–4t

U

–2t

U

0t

U

+2t

U

+4t

U

+6t

U

Divide by 4 Inverted

[1]

–6t

U

–4t

U

–2t

U

0t

U

+2t

U

+4t

U

+6t

U

Document Number: 38-07138 Rev. *B Page 3 of 19

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CY7B992

Figure 1 shows the typical outputs with FB connected to a zero skew output.

t

0

– 6t

U

t

0

– 5t

U

t

0

– 4t

U

t

0

– 3t

U

t

0

– 2t

U

t

0

– 1t

U

t 0t

0

+1t

U

t 0t 0t 0t 0t

0

+2tU+3tU+4tU+5tU+6t

U

FBInput

REFInput

– 6t

U

– 4t

U

– 3t

U

– 2t

U

– 1t

U

0t

U

+1t

U

+2t

U

+3t

U

+4t

U

+6t

U

DIVIDED

INVERT

LM

LH

(N/A)

ML

(N/A)

MM

(N/A)

MH

(N/A)

HL

HM

LL/HH

HH

3Fx
4Fx

(N/A)

LL

LM

LH

ML

MM

MH

HL

HM

HH

(N/A)

(N/A)

(N/A)

1Fx
2Fx

Note

4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

[4]

Test Mode

The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in “Skew Select

Matrix” on page 3. For testing purposes, any of the three level

inputs can have a removable jumper to ground, or be tied LOW
through a 100Ω resistor. This enables an external tester to
change the state of these pins.

Document Number: 38-07138 Rev. *B Page 4 of 19

If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.

In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (xF0 and xF1) and the waveform characteristics of
the REF input.

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CY7B992

Maximum Ratings

Note

5. Indicates case temperature.

Operating Range

Operating outside these boundaries affects the performance and
life of the device. These user guidelines are not tested.

Storage Temperature .................................–65

Ambient Temperature with

Power Applied ............................................–55

Supply Voltage to Ground Potential................–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

Output Current into Outputs (LOW).............................64 mA

Static Disc harge Voltage............................................>2001V

(MIL-STD-883, Method 3015)

Latch Up Current................................................ ... ..>200 mA

°C to +150°C

°C to +125°C

Range

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%

[5]

Military

[5]

Military

Ambient

Temperature V

–55°C to +125°C 5V ± 10%
–55°C to +125°C 5V ± 10%

CC

Document Number: 38-07138 Rev. *B Page 5 of 19

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CY7B992

Electrical Characteristics

Notes

6. For more information see “Group A Subgroup Testing” on page 17.

7. These inputs are normally wired to V

CC

, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold

unconnected inputs at V

CC

/2. If these inputs are switched, the f unction and timing of t he output s may glitch a nd the PLL may re quire an add itional t

LOCK

time before

all datasheet limits are achieved.

8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must
not be shorted to GND. Doing so may cause permanent damage.

9. T otal output current per output pairis approximated by the following expression that includes device current plus load current:
CY7B991: I

CCN

= [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1

CY7B992: I

CCN

= [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1

Where

F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F < C.

10.Total power dissipation per out put pair can be approximated b y the following expression that include s device power dissip ation plus power dissipati on due to the load
circuit:
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.

11.Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.

Over the Operating Range

Parameter Description Test Conditions Min Max Min Max Unit

V

V

V

V

V

V

V

I

IH

I

IL

I

IHH

I

IMM

I

ILL

I

OS

I

CCQ

I

CCN

OH

OL

IH

IL

IHH

IMM

ILL

Output HIGH Voltage VCC = Min IOH = –16 mA 2.4 V

Output LOW Voltage VCC = Min, IOL = 46 mA 0.45 V

Input HIGH Voltage
(REF and FB inputs only)

Input LOW Voltage
(REF and FB inputs only)

Three Level Input HIGH
Voltage (Test, FS, xFn)

Three Level Input MID
Voltage (Test, FS, xFn)

Three Level Input LOW
Voltage (Test, FS, xFn)

Input HIGH Leakage Current
(REF and FB inputs only)

Input LOW Leakage Current
(REF and FB inputs only)

Input HIGH Current
(Test, FS, xFn)

Input MID Current
(Test, FS, xFn)

Input LOW Current
(Test, FS, xFn)

Output Short Circuit
Current

Operating Current Used by
Internal Circuitry

Output Buffer Current per
Output Pair

PD Power Dissipation per

Output Pair

[6]

CY7B991 CY7B992

VCC = Min, IOH =–40 mA VCC–0.75

VCC = Min, IOL = 46 mA 0.45

2.0 V

CC

VCC –

1.35

V

CC

–0.5 0.8 –0.5 1.35 V

Min ≤ VCC ≤ Max VCC – 0.85 V

[10]

Min ≤ VCC ≤ Max VCC/2 –

[10]

Min ≤ VCC ≤

[10]

Maximum

500 mV

500 mV

0.0 0.85 0.0 0.85 V

VCC/2 +

VCC – 0.85 V

CC

VCC/2 –

500 mV

CC

VCC/2 +
500 mV

VCC = Max, VIN = Max. 10 10 μA

VCC = Max, VIN = 0.4V –500 –500 μA

VIN = V

CC

200 200 μA

VIN = VCC/2 –50 50 –50 50 μA

VIN = GND –200 –200 μA

[8]

VCC = Max, V
= GND (25

V

= V

CCN

All Input

CCQ

Selects Open
V

= V

[9]

[10]

CCN

I

= 0 mA

OUT

Input Selects Open, f
V

= V

CCN

I

= 0 mA

OUT

Input Selects Open, f

OUT

°C only)

= Max,

= Max,

CCQ

= Max,

CCQ

–250 N/A mA

Com’l 85 85 mA

Mil/Ind 90 90

14 19 mA

MAX

78 104

MAX

[11]

V

V

V

mW

Document Number: 38-07138 Rev. *B Page 6 of 19

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