• Package available in a standard 450-mil-wide (300-mil
body width) 28-lead narrow SOIC, 28-lead TSOP-1, and
reverse 28-lead TSOP-1 package
Logic Block Diagram
and OE features
Functional Description
[1]
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE
) and active LOW output enable (OE) and three-state
drivers. These devices have an automatic power-down
feature, reducing the power consumption by over 99% when
deselected.
An active LOW write enable signal (WE
writing/reading operation of the memory. When CE
) controls the
and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
through I/O7) is written into the memory location
0
addressed by the address present on the address pins (A
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE
while WE
remains inactive or HIGH. Under these conditions,
and OE active LOW,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE
) is HIGH.
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
INPUTBUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
3
2
ROW DECODER
A
A
CE
WE
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
512 × 512
ARRA
COLUMN
DECODER
14
A13A11A
A
Y
SENSE AMPS
POWER
DOWN
0
1
12
A
A
Cypress Semiconductor Corporation•3901 North First Street•San Jose•CA 95134•408-943-2600
Document #: 38-05057 Rev. *D Revised June 28, 2004
14GroundGND. Ground for the device
28Power SupplyVcc. Power supply for the device
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
-I/O7. Data lines. Used as input or output lines depending on operation
0
. When selected LOW, a WRITE is conducted. When selected HIGH, a READ
is conducted
. When LOW, selects the chip. When HIGH, deselects the chip
. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins