Page 1
CY62167G/CY62167GE MoBL
®
16-Mbit (1M words × 16-bit/2M words × 8-bit)
Static RAM with Error-Correcting Code (ECC)
16-Mbit (1M words × 16-bit/2M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for VCC range of 1.65 V–2.2 V), VCC=3V
(for V
CC
range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Features
■ Ultra-low standby current
❐ Typical standby current: 5.5 μA
❐ Maximum standby current: 16 μA
■ High speed: 45 ns/55 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■ 1.0-V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ 48-pin TSOP I package configurable as 1M × 16 or 2M × 8
SRAM
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY62167G and CY62167GE are high-performance CMOS,
low-power (MoBL
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62167GE device includes an
ERR pin that signals a single-bit error-detection and correction
event during a read cycle.
To access devices with a single chip enable input, assert the chip
enable (CE
assert both chip enable inputs – CE
To perform data writes, assert the Write Enable (WE
and provide the data and address on the device data pins (I/O
®
) SRAM devices with embedded ECC
[1]
. Both
) input LOW. To access dual chip enable devices,
as LOW and CE2 as HIGH.
1
) input LOW,
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE
controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE
provide the required address on the address lines. You can
access read data on the I/O lines (I/O
through I/O15). To perform
0
byte accesses, assert the required byte enable signal (BHE or
) to read either the upper byte or the lower byte of data from
BLE
the specified address location.
All I/Os (I/O
through I/O15) are placed in a high-impedance state
0
when the device is deselected (CE HIGH for a single chip enable
device and CE
HIGH / CE2 LOW for a dual chip enable device),
1
or the control signals are de-asserted (OE, BLE, BHE).
These devices have a unique Byte Power-down feature where,
if both the Byte Enables (BHE
and BLE) are disabled, the
devices seamlessly switch to the standby mode irrespective of
the state of the chip enables, thereby saving power.
On the CY62167GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the Truth Table
– CY62167G/CY62167GE on page 16 for a complete description
of read and write modes.
The CY62167G and CY62167GE devices are available in a
Pb-free 48-pin TSOP I package and 48-ball VFBGA packages.
The logic block diagrams are on page 2.
The device in the 48-pin TSOP I package can also be configured
to function as a 2M words × 8-bit device. Refer to the Pin
Configurations section for details.
For a complete list of related documentation, click here.
0
) input and
Product Portfolio
Features and
Options
Product
(see the Pin
Range VCC Range (V) Speed (ns)
Configurations
section)
CY62167G(E)18 Single or dual
CY62167G(E)30 2.2 V–3.6 V 45 29 36 5.5 16
CY62167G(E) 4.5 V–5.5 V
Chip Enables
Optional ERR pin
Industrial 1.65 V–2.2 V 55 29 32 7 26
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-81537 Rev. *P Revised May 26, 2017
Current Consumption
Operating ICC, (mA)
f = f
max
[2]
Typ
Max Typ
Standby, I
[2]
SB2
(µA)
Max
Page 2
CY62167G/CY62167GE MoBL
®
1M x 16 /
2M x 8
RAM ARRAY
ROW DECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN DECODER
A10
SENSE AMPS
ECC DECODE
A11
A12
A13
A14
A15
A16
A17
A18
A19
ECC ENCODE DATAIN DRIVERS
I/O0-I/O
7
I/O8-I/O
15
BHE
WE
OE
BLE
CE
2
CE
1
BYTE
POWER DOWN
CIRCUIT
CE
BHE
BLE
Logic Block Diagram – CY62167G
1M x 16 /
2M x 8
RAM ARRAY
ROW DECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN DECODER
A10
SENSE AMPS
ECC DECODE
A11
A12
A13
A14
A15
A16
A17
A18
A19
ECC ENCODE DATAIN DRIVERS
I/O0-I/O
7
I/O8-I/O
15
BHE
WE
OE
BLE
CE
2
CE
1
BYTE
POWER DOWN
CIRCUIT
CE
BHE
BLE
ERR
Logic Block Diagram – CY62167GE
Document Number: 001-81537 Rev. *P Page 2 of 23
Page 3
CY62167G/CY62167GE MoBL
®
Contents
Pin Configuration – CY62167G ........................................ 4
Pin Configuration – CY62167GE .....................................5
Maximum Ratings .............................................................7
Operating Range ...............................................................7
DC Electrical Characteristics ..........................................7
Capacitance ...................................................................... 9
Thermal Resistance ..........................................................9
AC Test Loads and Waveforms .......................................9
Data Retention Characteristics .....................................10
Data Retention Waveform ..............................................10
Switching Characteristics ..............................................11
Switching Waveforms ....................................................12
Truth Table – CY62167G/CY62167GE ........................... 16
ERR Output – CY62167GE .............................................16
Ordering Information ......................................................17
Ordering Code Definitions .........................................18
Package Diagrams ..........................................................19
Acronyms ........................................................................ 21
Document Conventions .................................................21
Units of Measure .......................................................21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products ....................................................................23
PSoC® Solutions ......................................................23
Cypress Developer Community .................................23
Technical Support ..................................................... 23
Document Number: 001-81537 Rev. *P Page 3 of 23
Page 4
CY62167G/CY62167GE MoBL
®
Pin Configuration – CY62167G
WE
A
11
A
10
A
6
A
0
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
Vss
A
7
I/O
0
BHE
CE
2
A
17
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
A
1
A
2
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE
2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE
1
A0
Notes
3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
4. Tie the BYTE
pin in the 48-pin TSOP I package to VCC to use the device as a 1 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2 M ×8 SRAM by
tying the BYTE
signal to VSS. In the 2 M ×8 configuration, pin 45 is the extra address line A20, while BHE, BLE, and I/O8 to I/O14 pins are not used and can be left floating.
Figure 1. 48-ball VFBGA Pinout (Dual Chip Enable without ERR) – CY62167G
[3]
Figure 2. 48-pin TSOP I Pinout (Dual Chip Enable without ERR) – CY62167G
Document Number: 001-81537 Rev. *P Page 4 of 23
[3, 4]
Page 5
CY62167G/CY62167GE MoBL
®
Pin Configuration – CY62167GE
WE
A
11
A
10
A
6
A
0
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
Vss
A
7
I/O
0
BHE
ERR
A
17
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
A
1
A
2
A
3
WE
A
11
A
10
A
6
A
0
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
Vss
A
7
I/O
0
BHE
CE
2
A
17
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
ERR
V
CC
A
1
A
2
A
3
Note
5. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
6. ERR is an Output pin. If not used, this pin should be left floating.
Figure 3. 48-ball VFBGA Pinout (Single Chip Enable with ERR) – CY62167GE
[5, 6]
Figure 4. 48-ball VFBGA Pinout (Dual Chip Enable with ERR) – CY62167GE
Document Number: 001-81537 Rev. *P Page 5 of 23
[5, 6]
Page 6
CY62167G/CY62167GE MoBL
®
Pin Configuration – CY62167GE (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE
2
ERR
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE
1
A0
Notes
7. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
8. Tie the BYTE
pin in the 48-pin TSOP I package to VCC to use the device as a 1 M ×16 SRAM. The 48-pin TSOP I package can also be used as a 2 M × 8 SRAM by
tying the BYTE
signal to VSS. In the 2 M × 8 configuration, pin 45 is the extra address line A20, while the BHE, BLE, and I/O8 to I/O14 pins are not used and can be
left floating.
Figure 5. 48-pin TSOP I Pinout (Dual Chip Enable with ERR) – CY62167GE
[7, 8]
Document Number: 001-81537 Rev. *P Page 6 of 23
Page 7
CY62167G/CY62167GE MoBL
®
Maximum Ratings
Notes
9. V
IL(min)
= –2.0 V and V
IH(max)
= VCC + 2 V for pulse durations of less than 20 ns.
10. Full device AC operation assumes a 100-µs ramp time from 0 to V
CC
(min) and 200-µs wait time after VCC stabilizes to its operational value.
11. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
12. This parameter is guaranteed by design and is not tested.
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage
to ground potential .............................. –0.5 V to V
DC voltage applied to outputs
in High Z state
[9]
.................................. –0.5 V to V
CC
CC
+ 0.5 V
+ 0.5 V
DC Electrical Characteristics
Over the operating range of –40 °C to 85 °C
DC input voltage
[9]
.............................. –0.5 V to V
CC
+ 0.5 V
Output current into outputs (LOW) .............................20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch-up current ..................................................... >140 mA
Operating Range
Grade Ambient Temperature V
Industrial –40 °C to +85 °C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
[10]
CC
4.5 V to 5.5 V
Parameter Description Test Conditions
V
OH
V
OL
V
IH
Output HIGH
voltage
Output LOW
voltage
Input HIGH
[9]
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V V
2.7 V to 3.6 V V
4.5 V to 5.5 V V
4.5 V to 5.5 V V
= Min, IOH = –0.1 mA 2.0 – –
CC
= Min, IOH = –1.0 mA 2.4 – –
CC
= Min, IOH = –1.0 mA 2.4 – –
CC
= Min, IOH = –0.1 mA VCC – 0.4
CC
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2
2.2 V to 2.7 V V
2.7 V to 3.6 V V
4.5 V to 5.5 V V
= Min, IOL = 0.1 mA – – 0.4
CC
= Min, IOL = 2.1 mA – – 0.4
CC
= Min, IOL = 2.1 mA – – 0.4
CC
1.65 V to 2.2 V – 1.4 – VCC + 0.2
2.2 V to 2.7 V – 1.8 – V
2.7 V to 3.6 V – 2.0 – V
4.5 V to 5.5 V – 2.2 – V
V
IL
Input LOW
[9]
voltage
1.65 V to 2.2 V – –0.2 – 0.4
2.2 V to 2.7 V – –0.3 – 0.6
2.7 V to 3.6 V – –0.3 – 0.8
4.5 V to 5.5 V – –0.5 – 0.8
I
I
I
IX
OZ
CC
Input leakage current GND < VIN < V
Output leakage current GND < V
VCC operating supply current VCC = Max, I
CMOS levels
OUT
OUT
CC
< VCC, Output disabled –1.0 – +1.0
= 0 mA,
45/55 ns
Min Typ
[12]
[11]
Max
––
+ 0.3
CC
+ 0.3
CC
+ 0.5
CC
–1.0 – +1.0 μA
f = 22.22 MHz
–29.036.0mA
(45 ns)
f = 18.18 MHz
–29.032.0
(55 ns)
f = 1 MHz – 7.0 9.0
Unit
Document Number: 001-81537 Rev. *P Page 7 of 23
Page 8
CY62167G/CY62167GE MoBL
®
DC Electrical Characteristics (continued)
Notes
13. Chip enables (CE
1
and CE2) and BYTE must be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
14. The I
SB2
maximum limits at 25 °C, 40 °C, and 70 °C are guaranteed by design and not 100% tested.
Over the operating range of –40 °C to 85 °C
Parameter Description Test Conditions
I
SB1
[13]
Automatic Power-down
Current – CMOS Inputs;
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > V
CC
– 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
Automatic Power-down
f = f
(address and data only),
max
f = 0 (OE, and WE), VCC = V
CE1 > VCC – 0.2V or
CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
I
SB2
[13]
Current – CMOS Inputs
V
= 1.65 V to 2.2 V
CC
Automatic Power-down
Current – CMOS Inputs
VCC = 2.2 V to 3.6 V and
4.5 V to 5.5 V
VIN > VCC – 0.2 V or
VIN < 0.2 V,
Automatic Power-down
f = 0, VCC = V
CE1 > VCC – 0.2 V or CE2 < 0.2 V
CC(max)
Current – CMOS Inputs
= 1.65 V to 2.2 V
V
CC
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = V
CC(max)
45/55 ns
Min Typ
[11]
–5.516.0
–7.026.0
CC(max)
25 °C – 5.5 6.5
40 °C – 6.3 8.0
70 °C – 8.4 12.0
85 °C – 12.0 16.0
–7.026.0
Max
[14]
[14]
Unit
μA
[14]
Document Number: 001-81537 Rev. *P Page 8 of 23
Page 9
CY62167G/CY62167GE MoBL
®
Capacitance
V
HIGH
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
TH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Note
15. Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
[15]
Description Test Conditions Max Unit
Input capacitance TA = 25 °C, f = 1 MHz, VCC = V
Output capacitance 10.0 pF
Thermal Resistance
Parameter
Θ
JA
Θ
JC
[15]
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Description Test Conditions 48-ball VFBGA 48-pin TSOP I Unit
AC Test Loads and Waveforms
CC(typ)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Figure 6. AC Test Loads and Waveforms
10.0 pF
31.50 57.99 °C/W
15.75 13.42 °C/W
Parameters 1.8 V 2.5 V 3.0 V 5.0 V Unit
R1 13500 16667 1103 1800 Ω
R2 10800 15385 1554 990 Ω
R
TH
V
TH
V
HIGH
Document Number: 001-81537 Rev. *P Page 9 of 23
6000 8000 645 639 Ω
0.80 1.20 1.75 1.77 V
1.8 2.5 3.0 5.0 V
Page 10
CY62167G/CY62167GE MoBL
®
Data Retention Characteristics
t
CDR
t
R
VDR = 1.0 V
DATA RETENTION MODE
V
CC
(min) V
CC
(min)
V
CC
CE
2
CE1 or
BHE. BLE
Notes
16. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
17. Chip enables (CE
1
and CE2) and BYTE must be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
18. I
CCDR
is guaranteed only after the device is first powered up to V
CC(min)
and then brought down to VDR.
19. These parameters are guaranteed by design and are not tested.
20. Full-device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
21. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[17, 18]
VCC for data retention – 1.0 – – V
Data retention current 1.2 V < V
> VCC − 0.2 V or CE2 < 0.2 V
CE
1
CC
< 2.2 V,
– 7.0 26.0 μA
or (BHE and BLE) > VCC – 0.2 V,
> VCC − 0.2 V or VIN < 0.2 V
V
IN
2.2 V < V
4.5 V < V
> VCC − 0.2 V or CE2 < 0.2 V
CE
1
< 3.6 V or
CC
< 5.5 V,
CC
– 5.5 16.0 μA
or (BHE and BLE) > VCC – 0.2 V,
> VCC − 0.2 V or VIN < 0.2 V
V
IN
[19]
t
CDR
[19, 20]
t
R
Chip deselect to data retention
–0.0–––
time
Operation recovery time – 45/55 – – ns
Data Retention Waveform
Figure 7. Data Retention Waveform
[21]
[16]
Max Unit
Document Number: 001-81537 Rev. *P Page 10 of 23
Page 11
CY62167G/CY62167GE MoBL
®
Switching Characteristics
Notes
22. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V
CC
> 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for V
CC
> 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading shown in Figure 6 on page 9, unless specified otherwise.
23. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
24. Tested initially and after any design or process changes that may affect these parameters.
25. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
26. These parameters are guaranteed by design and are not tested.
27. The internal write time of the memory is defined by the overlap of WE
= VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
28. The minimum write cycle pulse width for Write Cycle No. 1 (WE
Controlled, OE LOW) should be equal to the sum of t
HZWE
and tSD.
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[22]
Description
45 ns 55 ns
Min Max Min Max
Read cycle time 45.0 – 55.0 – ns
Address to data valid/Address to ERR valid – 45.0 – 55.0 ns
Data hold from address change/ERR hold from address
10.0 – 10.0 – ns
change
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR
– 45.0 – 55.0 ns
valid
OE LOW to data valid/OE LOW to ERR valid – 22.0 – 25.0 ns
OE LOW to Low Z
OE HIGH to High Z
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH and CE2 LOW to High Z
CE1 LOW and CE2 HIGH to power-up
CE1 HIGH and CE2 LOW to power-down
[23, 24]
[23, 24, 25]
[23, 24]
[23, 24, 25]
[26]
[26]
5.0 – 5.0 – ns
– 18.0 – 18.0 ns
10.0 – 10.0 – ns
– 18.0 – 18.0 ns
0.0 – 0.0 – ns
– 45.0 – 55.0 ns
BLE/BHE LOW to data valid – 45.0 – 55.0 ns
BLE/BHE LOW to Low Z
BLE/BHE HIGH to High Z
[27, 28]
[23]
[23, 25]
5.0 – 5.0 – ns
– 18.0 – 18.0 ns
Write cycle time 45.0 – 55.0 – ns
CE1 LOW and CE2 HIGH to write end 35.0 – 40.0 – ns
Address setup to write end 35.0 – 40.0 – ns
Address hold from write end 0 – 0 – ns
Address setup to write start 0 – 0 – ns
WE pulse width 35.0 – 40.0 – ns
BLE/BHE LOW to write end 35.0 – 40.0 – ns
Data setup to write end 25.0 – 25.0 – ns
Data hold from write end 0.0 – 0.0 – ns
WE LOW to High Z
WE HIGH to Low Z
[23, 24, 25]
[23, 24]
– 18.0 – 20.0 ns
10.0 – 10.0 – ns
Unit
Document Number: 001-81537 Rev. *P Page 11 of 23
Page 12
CY62167G/CY62167GE MoBL
®
Switching Waveforms
ADDRESS
DATA I/O
PREVIOUS DATA
OUT
VALID
DATA
OUT
VALID
t
RC
t
OHA
t
AA
ADDRESS
DATA I/O PREVIOUS DATA
OUT
VALID DATA
OUT
VALID
t
RC
t
OHA
t
AA
ERR PREVIOUS ERR VALID ERR VALID
t
OHA
t
AA
Notes
29. The device is continuously selected. OE
= VIL, CE = VIL, BHE or BLE, or both = VIL.
30. WE
is HIGH for read cycle.
Figure 8. Read Cycle No. 1 of CY62167G (Address Transition Controlled)
[29, 30]
Figure 9. Read Cycle No. 1 of CY62167GE (Address Transition Controlled)
[29, 30]
Document Number: 001-81537 Rev. *P Page 12 of 23
Page 13
CY62167G/CY62167GE MoBL
®
Switching Waveforms (continued)
t
RC
t
HZCE
t
PD
t
ACE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
DATA
OUT
VALID
HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE/
BLE
DA T A I/O
V
CC
SUPPLY
CURRENT
t
HZOE
t
HZBE
I
SB
ADDRESS
CE
DATA I/O
t
WC
t
SCE
t
HD
t
SD
t
BW
BHE/
BLE
t
AW
t
HA
t
SA
t
PWE
t
LZWE
t
HZWE
WE
DATAIN VALID
Note 36
Notes
31. WE
is HIGH for read cycle.
32. For all dual chip enable devices, CE
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE
is HIGH.
33. Address valid prior to or coincident with CE
LOW transition.
34. The internal write time of the memory is defined by the overlap of WE
= VIL, CE1 = VIL, BHE or BLE, or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
35. Data I/O is in the high-impedance state if CE
= VIH, or OE = VIH, or BHE, and/or BLE = VIH.
36. During this period, the I/Os are in the output state. Do not apply input signals.
37. The minimum write cycle pulse width should be equal to the sum of t
HZWE
and tSD.
Figure 10. Read Cycle No. 2 (OE Controlled)
[31, 32, 33, 35]
[32, 34, 35, 33]
Figure 11. Write Cycle No. 1 (WE Controlled, OE LOW)
Document Number: 001-81537 Rev. *P Page 13 of 23
Page 14
CY62167G/CY62167GE MoBL
®
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
t
WC
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
BW
t
HD
t
HZOE
t
SD
DATAIN VALID
Note 41
Notes
38. For all dual chip enable devices, CE
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE
is HIGH.
39. The internal write time of the memory is defined by the overlap of WE
= VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
40. Data I/O is in the high-impedance state if CE
= VIH, or OE = VIH, or BHE, and/or BLE = VIH.
41. During this period, the I/Os are in output state. Do not apply input signals.
Figure 12. Write Cycle No. 2 (CE Controlled)
[38, 39, 40]
Document Number: 001-81537 Rev. *P Page 14 of 23
Page 15
CY62167G/CY62167GE MoBL
®
Switching Waveforms (continued)
DATAIN VALID
ADDRESS
CE
WE
DATA I/O
t
WC
t
SCE
t
AW
t
SA
t
BW
t
HA
t
HD
t
HZWE
t
SD
BHE/
BLE
t
PWE
t
LZWE
Note 45
ADDRESS
CE
WE
BHE/BLE
DATA I/O
OE
t
WC
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
BW
t
HD
t
HZOE
t
SD
DATAIN VALID
Note 45
Notes
42. For all dual chip enable devices, CE
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE
is HIGH.
43. The internal write time of the memory is defined by the overlap of WE
= VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
44. Data I/O is in the high-impedance state if CE
= VIH, or OE = VIH, or BHE, and/or BLE = VIH.
45. During this period, the I/Os are in output state. Do not apply input signals.
Figure 13. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
[42, 43, 44]
[42, 43, 44]
Figure 14. Write Cycle No. 5 (WE Controlled)
Document Number: 001-81537 Rev. *P Page 15 of 23
Page 16
CY62167G/CY62167GE MoBL
®
Truth Table – CY62167G/CY62167GE
Notes
46. This pin is available only in the 48-pin TSOP I package. Tie the BYTE
to VCC to configure the device in the 1M ×16 option. The 48-pin TSOP I package can also be
used as a 2M × 8 SRAM by tying the BYTE
signal to VSS.
47. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
48. ERR is an Output pin. If not used, this pin should be left floating.
[46]
BYTE
[47]
X
XX
XX
H L H H L L L Data Out (I/O
HLHHLHL
HLHHLLH
H L H H H L H High-Z Output disabled Active (I
H L H H H H L High-Z Output disabled Active (I
H L H H H L L High-Z Output disabled Active (I
H L H L X L L Data In (I/O
HLHLXHL
HLHLXLH
L L H H L X X Data Out (I/O
L L H H H X X High-Z Output disabled Active (I
L L H L X X X Data In (I/O
CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power Configuration
[47]
HX
[47]
[47]X[47]
X X X X High-Z Deselect/Power-down Standby (ISB) 2M × 8/1M × 16
L X X X X High-Z Deselect/Power-down Standby (ISB) 2M × 8/1M × 16
X X H H High-Z Deselect/Power-down Standby (ISB)1M × 16
–I/O15)Read Active (I
0
Data Out (I/O
High-Z (I/O
High Z (I/O
Data Out (I/O
8
0
Data In (I/O
High-Z (I/O
High-Z (I/O
Data In (I/O
8
0
–I/O7);
0
–I/O15)
–I/O7);
–I/O15)
8
–I/O15) Write Active (ICC)1M × 16
0
–I/O7);
0
–I/O15)
–I/O7);
–I/O15)
8
–I/O7)ReadActive (I
0
–I/O7) Write Active (ICC)2M × 8
0
Read Active (I
Read Active (I
Write Active (I
Write Active (I
)1M × 16
CC
)1M × 16
CC
)1M × 16
CC
)1M × 16
CC
)1M × 16
CC
)1M × 16
CC
)1M × 16
CC
)1M × 16
CC
)2M × 8
CC
)2M × 8
CC
ERR Output – CY62167GE
Output
Document Number: 001-81537 Rev. *P Page 16 of 23
[48]
Mode
0 Read operation, no single-bit error in the stored data.
1 Read operation, single-bit error detected and corrected.
High-Z Device deselected / outputs disabled / Write operation
Page 17
CY62167G/CY62167GE MoBL
®
Ordering Information
Speed
(ns)
45 2.2 V–3.6 V CY62167GE30-45BV1XI 51-85150 48-ball VFBGA Sing Chip Enable Yes Industrial
55 1.65 V–2.2 V CY62167GE18-55BVXI 51-85150 48-ball VFBGA Dual Chip Enable Yes
Voltage
Range
CY62167GE30-45BV1XIT
CY62167GE30-45BVXI Dual Chip Enable Yes
CY62167GE30-45BVXIT
CY62167G30-45BVXI No
CY62167G30-45BVXIT
CY62167GE30-45ZXI 51-85183 48-pin TSOP I Dual Chip Enable Yes
CY62167GE30-45ZXIT
CY62167G30-45ZXI No
CY62167G30-45ZXIT
4.5 V–5.5 V CY62167G-45BVXI 51-85150 48-ball VFBGA Dual Chip Enable No
CY62167G-45BVXIT
CY62167G-45ZXI 51-85183 48-pin TSOP I Dual Chip Enable No
CY62167G-45ZXIT
CY62167GE-45ZXI Yes
CY62167GE-45ZXIT
CY62167GE18-55BVXIT
CY62167G18-55BVXI No
CY62167G18-55BVXIT
CY62167G18-55ZXI 51-85183 48-pin TSOP I No
CY62167G18-55ZXIT
Ordering Code
Package
Diagram
Package Type
(all Pb-free)
Key Features /
Differentiators
ERR Pin /
Ball
Operating
Range
Document Number: 001-81537 Rev. *P Page 17 of 23
Page 18
CY62167G/CY62167GE MoBL
®
Ordering Code Definitions
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade: X = I
I = Industrial
Pb-free
X = blank or 1
blank = Dual Chip Enable; 1 = Single Chip Enable
Package Type: XX = BV or Z
BV = 48-ball VFBGA; Z = 48-pin TSOP I
Speed Grade: XX = 45 or 55
45 = 45 ns; 55 = 55ns
Voltage Range: XX = 30 or blank or 18
30 = 3 V typ; blank = 5 V typ; 18 = 1.8 V typ
ERR output: Single-bit error correction indicator
Process Technology: G = 65 nm
Bus Width: 7 = × 16
Density: 6 = 16-Mbit
Family Code: 621 = MoBL
®
SRAM family
Company ID: CY = Cypress
CY
XX XX
621
6
7
G
X
-
X
XX
E
X
X
Document Number: 001-81537 Rev. *P Page 18 of 23
Page 19
CY62167G/CY62167GE MoBL
®
Package Diagrams
51-85150 *H
Figure 15. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
Document Number: 001-81537 Rev. *P Page 19 of 23
Page 20
CY62167G/CY62167GE MoBL
®
Package Diagrams (continued)
4
5
SEE DETAIL A
SEE DETAIL B
STANDARD PIN OUT (TOP VIEW)
REVERSE PIN OUT (TOP VIEW)
3
2X (N/2 TIPS)
B
B
N/2
0.20
D
D1
A
1
2
5
E
A
N/2 +1
2X
2X
B
N
0.10
0.10
SEATING PLANE
C
A1
e
9
2X (N/2 TIPS)
0.10 C
A2
DETAIL A
0.08MM M C A-B
SECTION B-B
7
c
b1
SEATING PLANE
PARALLEL TO
b
6
0°
DETAIL B
BASE METAL
e/2
X = A OR B
X
GAUGE PLAN
E
0.25 BASIC
WITH PLATING
7
L
C
R
(c)
8
c1
1
N
N/2
N/2 +1
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS (mm).
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
1.051.000.95
A2
N
R
0
L
e
c
D1
E
D
b
c1
b1
0.50 BASIC
0.60
0°
0.08
0.50
48
0.20
8
0.70
0.22
0.20
20.00 BASIC
18.40 BASIC
12.00 BASIC
0.10
0.17
0.10
0.17
0.21
0.27
0.16
0.23
A1
A
0.05
0.15
1.20
SYMBOL
MIN. MAX.
DIMENSIONS
NOM.
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
0.10mm AND 0.25mm FROM THE LEAD TIP.
SEATING PLANE.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Figure 16. 48-pin TSOP I (18.4 × 12 × 1.2 mm) Package Outline, 51-85183
Document Number: 001-81537 Rev. *P Page 20 of 23
Page 21
CY62167G/CY62167GE MoBL
®
Acronyms Document Conventions
Acronym Description
BHE Byte High Enable
BLE
CE
CMOS Complementary metal oxide semiconductor
I/O Input/output
OE
SRAM Static random access memory
TSOP Thin small outline package
VFBGA Very fine-pitch ball grid array
WE
Byte Low Enable
Chip Enable
Output Enable
Write Enable
Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
μA microampere
μs microsecond
mA milliampere
mm millimeter
ns nanosecond
Ω ohm
% percent
pF picofarad
V volt
W watt
Document Number: 001-81537 Rev. *P Page 21 of 23
Page 22
CY62167G/CY62167GE MoBL
®
Document History Page
Document Title: CY62167G/CY62167GE MoBL®, 16-Mbit (1M words × 16-bit/2M words × 8-bit) Static RAM with
Error-Correcting Code (ECC)
Document Number: 001-81537
Rev. ECN No.
*M 4791835 NILE 06/15/2015 Changed status from Preliminary to Final.
*N 5027105 NILE 11/25/2015 Updated DC Electrical Characteristics:
*O 5439177 VINI 09/16/2016 Updated DC Electrical Characteristics:
*P 5751153 VINI 05/26/2017 Updated Package Diagrams:
Orig. of
Change
Submission
Date
Description of Change
Changed minimum value of V
corresponding to Operating Range “2.7 V to 3.6 V” and
Test Condition “V
Changed minimum value of V
corresponding to Operating Range “2.2 V to 2.7 V”.
Updated Note 9 (Replaced 2 ns with 20 ns).
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Completing Sunset Review.
= Min, IOH = –1.0 mA”.
CC
parameter from 2.2 V to 2.4 V
OH
parameter from 2.0 V to 1.8 V
IH
Document Number: 001-81537 Rev. *P Page 22 of 23
Page 23
CY62167G/CY62167GE MoBL
®
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© Cypress Semiconductor Corporation, 2012–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-81537 Rev. *P Revised May 26, 2017 Page 23 of 23
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