Cypress CY62167EV30 User Manual
CY62167EV30 MoBL
®
16-Mbit (1M x 16 / 2M x 8) Static RAM
Features
1M × 16 / 2M x 8
RAM Array
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A12A13A14A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO8–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
CE
2
CE
1
A
19
BYTE
Power Down
Circuit
BHE
BLE
CE
2
CE
1
Logic Block Diagram
■ TSOP I Package Configurable as 1M x 16 or 2M x 8 SRAM
■ Very High Speed: 45 ns
■ Temperature Ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
■ Wide Voltage Range: 2.20V to 3.60V
■ Ultra Low Standby Power
❐ Typical standby current: 1.5 μA
❐ Maximum standby current: 12 μA
■ Ultra Low Active Power
❐ Typical active current: 2.2 mA @ f = 1 MHz
■ Easy Memory Expansion with CE
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I
, CE2, and OE Features
1
Packages
Functional Description
The CY62167EV30 is a high performance CMOS static RAM
organized as 1M words by 16 bits or 2M words by 8 bits. This
device features an advanced circuit design that provides an ultra
low active current. Ultra low active current is ideal for providing
More Battery Life™ (MoBL
®
) in portable applications such as
cellular telephones. The device also has an automatic power
down feature that reduces power consumption by 99 percent
when addresses are not toggling. Place the device into standby
mode when deselected (CE1 HIGH or CE2 LOW or both BHE and
BLE
are HIGH). The input and output pins (I/O0 through I/O15)
are placed in a high impedance state when: the device is
deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are disabled
(BHE
, BLE HIGH), or a write operation is in progress (CE1 LOW,
HIGH and WE LOW).
CE
2
To write to the device, take Chip Enables (CE1 LOW and CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A
). If Byte High Enable (BHE) is LOW, then data from the I/O
A
19
pins (I/O
the address pins (A
To read from the device, take Chip Enables (CE
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE
through I/O15) is written into the location specified on
8
through A19).
0
1
) HIGH. If Byte Low Enable (BLE) is LOW, then data
through
0
LOW and CE
from the memory location specified by the address pins appears
on I/O
to I/O7. If Byte High Enable (BHE) is LOW, then data from
0
memory appears on I/O
page 9 for a complete description of read and write modes.
to I/O15. See the “Truth Table” on
8
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
2
2
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05446 Rev. *E Revised March 23, 2009
[+] Feedback
CY62167EV30 MoBL
®
Pin Configuration
WE
A
11
A
10
A
6
A
0
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
Vss
A
7
I/O
0
BHE
CE
2
A
17
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
CC
A
1
A
2
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE
2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
IO15/A20
IO7
IO14
IO6
IO13
IO5
IO12
IO4
Vcc
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
OE
Vss
CE
1
A0
Notes
1. The information related to 6 x 7 x 1 mm VFBGA package is preliminary.
2. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.
3. NC pins are not connected on the die.
4. The BYTE
pin in the 48-TSOPI package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8 SRAM
by tying the BYTE
signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and IO8 to IO14 pins are not used.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= VCC(typ), TA = 25°C.
Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View
[1, 2, 3]
Figure 2. 48-Pin TSOP I Top View
Product Portfolio
Min Typ
Product VCC Range (V)
Range Operating I
CY62167EV30LL Industrial/Auto-A 2.2 3.0 3.6 45 2.2 4.0 25 30 1.5 12
Document #: 38-05446 Rev. *E Page 2 of 14
Speed
(ns)
[5]
Max Typ
[3, 4]
Power Dissipation
(mA)
CC
f = 1 MHz f = f
[5]
Max Typ
max
[5]
Max Typ
Standby I
(μA)
[5]
SB2
Max
[+] Feedback
CY62167EV30 MoBL
®
Maximum Ratings
Notes
6. V
IL
(min) = –2.0V for pulse durations less than 20 ns.
7. V
IH
(max) = VCC + 0.75V for pulse durations less than 20 ns.
8. Full Device AC operation assumes a 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after VCC stabilization.
9. Under DC conditions the device meets a V
IL
of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V. This is
applicable to TSOP I package only.
10. Only chip enables (CE
1
and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential .................................–0.3V to 3.9V V
DC Voltage Applied to Outputs
in High Z State
[6, 7]
..................–0.3V to 3.9V V
CC(max)
CC(max)
+ 0.3V
+ 0.3V
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Device Range
CY62167EV30LL Industrial/
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
[10]
Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 V
VCC < 3.6 IOH = –1.0 mA 2.4 V
2.7 <
Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V
VCC < 3.6 IOL = 2.1mA 0.4 V
2.7 <
Input HIGH Voltage 2.2 < VCC < 2.7 1.8 V
VCC < 3.6 2.2 V
2.7 <
Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 V
VCC < 3.6 For VFBGA package –0.3 0.8 V
2.7 <
For TSOP I package –0.3 0.7
Input Leakage Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 μA
VCC Operating Supply
Current
Automatic CE Power Down
Current—CMOS Inputs
Automatic CE Power Down
Current—CMOS Inputs
f = f
f = 1 MHz 2.2 4.0 mA
MAX
= 1/t
RC
VCC = VCC(max)
I
= 0 mA
OUT
CMOS levels
CE1 > VCC − 0.2V or CE2 < 0.2V
> VCC − 0.2V, V
V
IN
f = f
f = 0 (OE
(Address and Data Only),
MAX
, WE, BHE and BLE), VCC=3.60V
< 0.2V,
IN
CE1 > VCC − 0.2V or CE2 < 0.2V,
> VCC − 0.2V or VIN < 0.2V,
V
IN
f = 0, V
= 3.60V
CC
[6, 7]
...........–0.3V to 3.9V (VCC(max) + 0.3V
Ambient
Temperature
–40°C to +85°C 2.2V to 3.6V
Auto-A
45 ns (Industrial/Auto-A)
Min Typ
[5]
Max
+ 0.3V V
CC
+ 0.3V V
CC
–1 +1 μA
25 30 mA
1.5 12 μA
1.5 12 μA
[8]
V
CC
Unit
[9]
V
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Document #: 38-05446 Rev. *E Page 3 of 14
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
V
= V
CC
CC(typ)
10 pF
[+] Feedback
CY62167EV30 MoBL
®
Thermal Resistance
VCC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V
CC
ramp from V
DR
to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
13. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
VCC(min)
VCC(min)
t
CDR
VDR
>
1.5 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE.BLE
CE
2
or
[13]
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
Θ
Θ
Shaded areas contain preliminary information.
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
Figure 3. AC Test Loads and Waveforms
Parameters 2.2V to 2.7V 2.7V to 3.6V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
VFBGA
(6 x 7 x 1mm)
27.74 55 60 °C/W
9.84 16 4.3 °C/W
VFBGA
(6 x 8 x 1mm)
TSOP I Unit
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[11]
t
CDR
[12]
t
R
Document #: 38-05446 Rev. *E Page 4 of 14
VCC for Data Retention 1.5 V
[10]
Data Retention Current V
= 1.5V to 3.0V, CE1 > VCC − 0.2V, CE2
CC
< 0.2V, VIN > VCC − 0.2V or VIN < 0.2V
= 1.5V, CE1 > VCC − 0.2V, CE2 < 0.2V,
V
CC
V
> VCC − 0.2V or VIN < 0.2V
IN
Industrial/
Auto-A
Industrial -45BAXI/
Chip Deselect to Data
Retention Time
Operation Recovery Time t
Figure 4. Data Retention Waveform
-45ZXI
(TSOP I)
-45BVXI/
-45BVI
(VFBGA)
[5]
Max Unit
8 μA
10 μA
0ns
RC
ns
[+] Feedback
CY62167EV30 MoBL
®
Switching Characteristics
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of V
CC
(typ)/2, input pulse levels of 0
to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
15. AC timing parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
16. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
17. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE
, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
Over the Operating Range
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[18]
[14, 15]
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid 45 ns
OE LOW to Data Valid 22 ns
OE LOW to LOW Z
OE HIGH to High Z
[16]
[16, 17]
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH and CE2 LOW to High Z
CE1 LOW and CE2 HIGH to Power Up 0 ns
CE1 HIGH and CE2 LOW to Power Down 45 ns
BLE / BHE LOW to Data Valid 45 ns
BLE / BHE LOW to Low Z
BLE / BHE HIGH to HIGH Z
[16]
[16, 17]
Write Cycle Time 45 ns
CE1 LOW and CE2 HIGH to Write End 35 ns
Address Setup to Write End 35 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 35 ns
BLE / BHE LOW to Write End 35 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[16, 17]
[16]
[16]
[16, 17]
45 ns (Industrial/Auto-A)
Min Max
Unit
5ns
18 ns
10 ns
18 ns
10 ns
18 ns
18 ns
10 ns
Document #: 38-05446 Rev. *E Page 5 of 14
[+] Feedback
Loading...