Cypress CY62167EV18 User Manual
CY62167EV18 MoBL
®
16 Mbit (1M x 16) Static RAM
Features
Power Down
Circuit
BHE
BLE
CE
2
CE
1
1M × 16
RAM ARRAY
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A12A13A14A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO8–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
CE
2
CE
1
A
19
Logic Block Diagram
■ Very high speed: 55 ns
■ Wide voltage range: 1.65V to 2.25V
■ Ultra low standby power
❐ Typical standby current: 1.5 μA
❐ Maximum standby current: 12 μA
■ Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■ Easy memory expansion with CE
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in Pb-free 48-ball VFBGA packages
, CE2, and OE features
1
Functional Description
The CY62167EV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
®
) in portable
by 99 percent when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE
and BLE are HIGH). The input and output pins (I/O
through I/O15) are placed in a high impedance state when: the
device is deselected (CE
disabled (OE
HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE
in progress (CE
LOW, CE2 HIGH and WE LOW).
1
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
) is LOW, then data from I/O pins (I/O0 through I/O7) is
(BLE
written into the location specified on the address pins (A
A
). If Byte High Enable (BHE) is LOW, then data from I/O pins
19
through I/O15) is written into the location specified on the
(I/O
8
address pins (A
through A19).
0
To read from the device, take Chip Enables (CE
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then data
HIGH or CE2 LOW); outputs are
1
, BLE HIGH); and a write operation is
LOW and CE
1
through
0
LOW and CE
1
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
9 for a complete description of read and write modes.
to I/O15. See the Truth Table on page
8
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
0
2
2
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05447 Rev. *G Revised March 13, 2009
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CY62167EV18 MoBL
®
Pin Configuration
WE
A
11
A
10
A
6
A
0
A
3
CE
1
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
Vss
A
7
IO
0
BHE
CE
2
A
17
A
2
A
1
BLE
V
CC
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
cc
Notes
1. The information related to 6 x 7 x 1 mm VFBGA package is preliminary.
2. NC pins are not connected on the die.
3. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
5. This part can be operated in the V
CC
range of 1.65V–2.25V at 55ns speed. It can also be operated in the VCC range of 2.2V–3.6V at 45ns speed.
Product Portfolio
Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View
[1, 2, 3]
Power Dissipation
Product VCC Range (V)
Min Typ
[4]
Max Typ
Speed
(ns)
Operating I
CC
(mA)
f = 1 MHz f = f
[4]
Max Typ
[4]
max
Max Typ
Standby I
[4]
SB2
Max
CY62167EV18LL 1.65 1.8 2.25 55 2.2 4.0 25 30 1.5 12
CY62167EV30LL
[5]
(μA)
Document #: 38-05447 Rev. *G Page 2 of 13
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CY62167EV18 MoBL
®
Maximum Ratings
Notes
6. V
IL
(min) = –2.0V for pulse durations less than 20 ns.
7. V
IH
(max) = VCC + 0.75V for pulse durations less than 20 ns.
8. Full Device AC operation is based on a 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after VCC stabilization.
9. Only chip enables (CE
1
and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential .......................... –0.2V to 2.45V (V
DC Voltage Applied to Outputs
in High Z State
[6, 7]
........... –0.2V to 2.45V (VCC(max) + 0.2V)
(max) + 0.2V)
CC
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Device Range
CY62167EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
[9]
Output HIGH Voltage IOH = –0.1 mA 1.4 V
Output LOW Voltage IOL = 0.1 mA 0.2 V
Input HIGH Voltage V
Input LOW Voltage V
Input Leakage Current GND < VI < V
= 1.65V to 2.25V 1.4 V
CC
= 1.65V to 2.25V –0.2 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 μA
VCC Operating Supply
Current
f = f
= 1/t
max
RC
f = 1 MHz 2.2 4.0 mA
VCC = VCC(max)
= 0 mA
I
OUT
CMOS levels
Automatic CE Power Down
Current – CMOS Inputs
Automatic CE Power Down
Current – CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
> VCC – 0.2V, V
V
IN
(Address and Data Only),
f = f
max
f = 0 (OE
V
CC
, WE, BHE and BLE),
= VCC(max)
< 0.2V)
IN
CE1 > VCC – 0.2V or CE2 < 0.2V,
> VCC – 0.2V or VIN < 0.2V,
V
IN
CC
= V
CC(max)
f = 0, V
[6, 7]
....... –0.2V to 2.45V (VCC(max) + 0.2V)
Ambient
Temperature
55 ns
Min Typ
[4]
Max
+ 0.2V V
CC
–1 +1 μA
25 30 mA
1.5 12 μA
1.5 12 μA
[8]
V
CC
Unit
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Document #: 38-05447 Rev. *G Page 3 of 13
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
V
= V
CC
CC(typ)
10 pF
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CY62167EV18 MoBL
®
Thermal Resistance
VCC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V
CC
ramp from V
DR
to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
12. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
VCC(min)
VCC(min)
t
CDR
VDR
>
1.0 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE.BLE
CE
2
or
[12]
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Parameters 1.8V Unit
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
Figure 2. AC Test Loads and Waveforms
R1 13500 Ω
R2 10800 Ω
R
TH
V
TH
6000 Ω
0.80 V
VFBGA
(6 x 7 x 1mm)
VFBGA
(6 x 8 x 1mm)
27.74 55 °C/W
9.84 16 °C/W
Unit
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
[9]
I
CCDR
[10]
t
CDR
[11]
t
R
Document #: 38-05447 Rev. *G Page 4 of 13
VCC for Data Retention 1.0 V
Data Retention Current V
= 1.0V, CE1 > VCC – 0.2V, CE2 < 0.2V,
CC
> VCC – 0.2V or VIN < 0.2V
V
IN
Chip Deselect to Data
Retention Time
Operation Recovery Time t
Figure 3. Data Retention Waveform
[4]
Max Unit
10 μA
0ns
RC
ns
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