CY62167EV18 MoBL
®
16 Mbit (1M x 16) Static RAM
Features
Power Down
Circuit
BHE
BLE
CE
2
CE
1
1M × 16
RAM ARRAY
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A12A13A14A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO8–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
CE
2
CE
1
A
19
Logic Block Diagram
■ Very high speed: 55 ns
■ Wide voltage range: 1.65V to 2.25V
■ Ultra low standby power
❐ Typical standby current: 1.5 μA
❐ Maximum standby current: 12 μA
■ Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■ Easy memory expansion with CE
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in Pb-free 48-ball VFBGA packages
, CE2, and OE features
1
Functional Description
The CY62167EV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
®
) in portable
by 99 percent when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE
and BLE are HIGH). The input and output pins (I/O
through I/O15) are placed in a high impedance state when: the
device is deselected (CE
disabled (OE
HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE
in progress (CE
LOW, CE2 HIGH and WE LOW).
1
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
) is LOW, then data from I/O pins (I/O0 through I/O7) is
(BLE
written into the location specified on the address pins (A
A
). If Byte High Enable (BHE) is LOW, then data from I/O pins
19
through I/O15) is written into the location specified on the
(I/O
8
address pins (A
through A19).
0
To read from the device, take Chip Enables (CE
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then data
HIGH or CE2 LOW); outputs are
1
, BLE HIGH); and a write operation is
LOW and CE
1
through
0
LOW and CE
1
from the memory location specified by the address pins appears
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
9 for a complete description of read and write modes.
to I/O15. See the Truth Table on page
8
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
0
2
2
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05447 Rev. *G Revised March 13, 2009
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CY62167EV18 MoBL
®
Pin Configuration
WE
A
11
A
10
A
6
A
0
A
3
CE
1
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
Vss
A
7
IO
0
BHE
CE
2
A
17
A
2
A
1
BLE
V
CC
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
NC
V
cc
Notes
1. The information related to 6 x 7 x 1 mm VFBGA package is preliminary.
2. NC pins are not connected on the die.
3. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
5. This part can be operated in the V
CC
range of 1.65V–2.25V at 55ns speed. It can also be operated in the VCC range of 2.2V–3.6V at 45ns speed.
Product Portfolio
Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View
[1, 2, 3]
Power Dissipation
Product VCC Range (V)
Min Typ
[4]
Max Typ
Speed
(ns)
Operating I
CC
(mA)
f = 1 MHz f = f
[4]
Max Typ
[4]
max
Max Typ
Standby I
[4]
SB2
Max
CY62167EV18LL 1.65 1.8 2.25 55 2.2 4.0 25 30 1.5 12
CY62167EV30LL
[5]
(μA)
Document #: 38-05447 Rev. *G Page 2 of 13
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CY62167EV18 MoBL
®
Maximum Ratings
Notes
6. V
IL
(min) = –2.0V for pulse durations less than 20 ns.
7. V
IH
(max) = VCC + 0.75V for pulse durations less than 20 ns.
8. Full Device AC operation is based on a 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after VCC stabilization.
9. Only chip enables (CE
1
and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground
Potential .......................... –0.2V to 2.45V (V
DC Voltage Applied to Outputs
in High Z State
[6, 7]
........... –0.2V to 2.45V (VCC(max) + 0.2V)
(max) + 0.2V)
CC
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Device Range
CY62167EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
[9]
Output HIGH Voltage IOH = –0.1 mA 1.4 V
Output LOW Voltage IOL = 0.1 mA 0.2 V
Input HIGH Voltage V
Input LOW Voltage V
Input Leakage Current GND < VI < V
= 1.65V to 2.25V 1.4 V
CC
= 1.65V to 2.25V –0.2 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 μA
VCC Operating Supply
Current
f = f
= 1/t
max
RC
f = 1 MHz 2.2 4.0 mA
VCC = VCC(max)
= 0 mA
I
OUT
CMOS levels
Automatic CE Power Down
Current – CMOS Inputs
Automatic CE Power Down
Current – CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
> VCC – 0.2V, V
V
IN
(Address and Data Only),
f = f
max
f = 0 (OE
V
CC
, WE, BHE and BLE),
= VCC(max)
< 0.2V)
IN
CE1 > VCC – 0.2V or CE2 < 0.2V,
> VCC – 0.2V or VIN < 0.2V,
V
IN
CC
= V
CC(max)
f = 0, V
[6, 7]
....... –0.2V to 2.45V (VCC(max) + 0.2V)
Ambient
Temperature
55 ns
Min Typ
[4]
Max
+ 0.2V V
CC
–1 +1 μA
25 30 mA
1.5 12 μA
1.5 12 μA
[8]
V
CC
Unit
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Document #: 38-05447 Rev. *G Page 3 of 13
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
V
= V
CC
CC(typ)
10 pF
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CY62167EV18 MoBL
®
Thermal Resistance
VCC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V
CC
ramp from V
DR
to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
12. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
VCC(min)
VCC(min)
t
CDR
VDR
>
1.0 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE.BLE
CE
2
or
[12]
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Parameters 1.8V Unit
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
Figure 2. AC Test Loads and Waveforms
R1 13500 Ω
R2 10800 Ω
R
TH
V
TH
6000 Ω
0.80 V
VFBGA
(6 x 7 x 1mm)
VFBGA
(6 x 8 x 1mm)
27.74 55 °C/W
9.84 16 °C/W
Unit
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
[9]
I
CCDR
[10]
t
CDR
[11]
t
R
Document #: 38-05447 Rev. *G Page 4 of 13
VCC for Data Retention 1.0 V
Data Retention Current V
= 1.0V, CE1 > VCC – 0.2V, CE2 < 0.2V,
CC
> VCC – 0.2V or VIN < 0.2V
V
IN
Chip Deselect to Data
Retention Time
Operation Recovery Time t
Figure 3. Data Retention Waveform
[4]
Max Unit
10 μA
0ns
RC
ns
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CY62167EV18 MoBL
®
Switching Characteristics
Notes
13. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
CC(typ)
, and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4.
14. AC timing parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
16. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the output enters a high impedance state.
17. The internal memory write time is defined by the overlap of WE
, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Over the Operating Range
[13, 14]
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time 55 ns
Address to Data Valid 55 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid 55 ns
OE LOW to Data Valid 25 ns
OE LOW to Low-Z
OE HIGH to High-Z
[15]
[15, 16]
CE1 LOW and CE2 HIGH to Low-Z
CE1 HIGH and CE2 LOW to High-Z
CE1 LOW and CE2 HIGH to Power Up 0 ns
CE1 HIGH and CE2 LOW to Power Down 55 ns
BLE/BHE LOW to Data Valid 55 ns
BLE/BHE LOW to Low-Z
BLE/BHE HIGH to High-Z
[17]
[15]
[15, 16]
Write Cycle Time 55 ns
CE1 LOW and CE2 HIGH to Write End 40 ns
Address Setup to Write End 40 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 40 ns
BLE/BHE LOW to Write End 40 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[15, 16]
[15]
[15]
[15, 16]
55 ns
Min Max
Unit
5ns
18 ns
10 ns
18 ns
10 ns
18 ns
20 ns
10 ns
Document #: 38-05447 Rev. *G Page 5 of 13
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CY62167EV18 MoBL
®
Switching Waveforms
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
t
RC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
PD
t
HZBE
t
LZBE
t
HZCE
t
DBE
OE
CE
1
ADDRESS
CE
2
BHE/BLE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH
I
CC
I
SB
IMPEDANCE
Notes
18. The device is continuously selected. OE
, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.
19. WE
is HIGH for read cycle.
20. Address valid before or similar to CE
1
, BHE, BLE transition LOW and CE2 transition HIGH.
Figure 4 shows address transition controlled read cycle waveforms.
Figure 4. Read Cycle No. 1
[18, 19]
Figure 5 shows OE
controlled read cycle waveforms.
Figure 5. Read Cycle No. 2
[19, 20]
Document #: 38-05447 Rev. *G Page 6 of 13
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CY62167EV18 MoBL
®
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
VALID DATA
t
BW
NOTE 23
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
BHE/BLE
Notes
21. Data IO is high impedance if OE
= VIH.
22. If CE
1
goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
23. During this period the IOs are in output state. Do not apply input signals.
Figure 6 shows WE
controlled write cycle waveforms.
[17, 21, 22]
Figure 6. Write Cycle No. 1
Document #: 38-05447 Rev. *G Page 7 of 13
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CY62167EV18 MoBL
®
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
VALID DATA
t
BW
t
SA
NOTE 23
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
BHE/BLE
VAL I D DATA
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 23
CE
1
ADDRESS
CE
2
WE
DATA I/O
BHE
/BLE
Figure 7 shows CE
or CE2 controlled write cycle waveforms.
1
[17, 21, 22]
Figure 7. Write Cycle No. 2
Figure 8 shows WE controlled, OE LOW write cycle waveforms.
[22]
Figure 8. Write Cycle No. 3
Document #: 38-05447 Rev. *G Page 8 of 13
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CY62167EV18 MoBL
®
Switching Waveforms (continued)
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
VAL I D DATA
t
BW
t
SCE
t
PWE
NOTE 23
CE
1
ADDRESS
CE
2
WE
DATA IO
BHE
/BLE
Figure 9 shows BHE
/BLE controlled, OE LOW write cycle waveforms.
[22]
Figure 9. Write Cycle No. 4
Truth Table
CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power
HXXXXXHigh Z Deselect / Power Down Standby (I
XLXXXXHigh Z Deselect / Power Down Standby (I
XXXXHHHigh Z Deselect / Power Down Standby (I
–I/O15) Read Active (ICC)
0
–I/O7);
0
–I/O15)
8
Read Active (I
Read Active (I
–I/O15)
8
–I/O15) Write Active (ICC)
0
Write Active (I
Write Active (I
–I/O7);
0
–I/O15)
8
–I/O7);
0
–I/O15)
8
L H H L L L Data Out (I/O
L H H L H L Data Out (I/O
High Z (I/O
LHHLLHHigh Z (I/O0–I/O7);
Data Out (I/O
L H H H L H High Z Output Disabled Active (ICC)
LHHHHLHigh Z Output Disabled Active (I
L H H H L L High Z Output Disabled Active (I
L H L X L L Data In (I/O
L H L X H L Data In (I/O
High Z (I/O
LHLXLHHigh Z (I/O
Data In (I/O
CC
CC
CC
CC
CC
CC
SB
SB
SB
)
)
)
)
)
)
)
)
)
Document #: 38-05447 Rev. *G Page 9 of 13
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CY62167EV18 MoBL
®
Ordering Information
Speed
(ns) Ordering Code
CY62167EV18LL-55BAXI 001-13297 48-ball VFBGA (6 × 7 × 1 mm) (Pb-free) Industrial
55
CY62167EV18LL-55BVI 51-85150 48-ball VFBGA (6 × 8 × 1 mm)
CY62167EV18LL-55BVXI 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free)
CY62167EV30LL-45BVI
Package Diagram
[5]
Package
Diagram
51-85150 48-ball VFBGA (6 × 8 × 1 mm)
Package Type
Figure 10. 48-Ball VFBGA (6 x 7 x 1 mm), 001-13297
Operating
Range
NOTES:
1. ALL DIMENSION ARE IN MM [MAX/MIN]
2. JEDEC REFERENCE : MO-216
3. PACKAGE WEIGHT : 0.03g
001-13297-*A
Document #: 38-05447 Rev. *G Page 10 of 13
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CY62167EV18 MoBL
®
Package Diagram
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
Document #: 38-05447 Rev. *G Page 11 of 13
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CY62167EV18 MoBL
®
Document History Page
Document Title: CY62167EV18 MoBL® 16 Mbit (1M x 16) Static RAM
Document Number: 38-05447
REV. ECN NO.
Orig. of
Change
** 202600 AJU 01/23/2004 New Data Sheet
*A 463674 NXR See ECN Converted from Advance Information to Preliminary
*B 469182 NSI See ECN Minor Change: Moved to external web
*C 619122 NXR See ECN Replaced 45 ns speed bin with 55 ns speed bin
*D 1130323 VKN See ECN Converted from preliminary to final
*E 1388287 VKN See ECN Added 48-Ball VFBGA (6 x 7 x 1mm) package
*F 1664843 VKN/AESA See ECN Added CY62167EV30LL-45BVI part in the Ordering Information table
*G 2675375 VKN/PYRS 03/17/2009 Added CY62167EV18LL-55BVI part in the Ordering Information table
Submission
date Description of Change
Changed V
Removed ‘L’ bin and 35 ns speed bin from product offering
CC(max)
Changed ball E3 from DNU to NC
Removed redundant foot note on DNU
Changed the I
Changed the I
Changed the AC Test Load Capacitance value from 50 pF to 30 pF
SB2(typ)
CC(max)
Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns
Changed the I
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Updated 48 ball FBGA Package Information
CCDR
, t
OHA
from 3 ns to 5 ns
LZOE
, t
HZOE
, tAW, and t
SCE
from 30 ns to 35 ns
PE
from 20 ns to 25 ns
SD
Updated the Ordering Information table
Added footnote# 8 related I
Changed I
Changed I
Added footnote# 13 related AC timing parameters
Changed t
Changed t
Changed t
and I
SB1
CCDR
spec from 45 ns to 55 ns
WC
, tAW, t
SCE
HZWE
Added footnote# 1 related to FBGA package
Updated Ordering Information table
Added footnote# 5 related to CY62167EV30LL-45BVI part
from 2.20V to 2.25V
value from 1.3 μA to 1.5 μA
value from 40 mA to 25 mA
Value from 8 μA to 5 μA
, t
LZCE
HZCE
spec from 8 μA to 10 μA
spec from 18 ns to 20 ns
, and t
LZBE
, t
, and t
HZBE
from 40 ns to 35 ns
BW
SB2
spec from 10 μA to 12 μA
SB2
, tBW spec from 35 ns to 40 ns
PWE
from 6 ns to 10 ns
LZWE
from 15 ns to 18 ns
HZWE
and I
CCDR
Document #: 38-05447 Rev. *G Page 12 of 13
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CY62167EV18 MoBL
®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05447 Rev. *G Revised March 13, 2009 Page 13 of 13
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trad emarks of their respective holders.
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