CY62167DV18 MoBL
®
16-Mbit (1M x 16) Static RAM
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–1.95V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = f
max
• Ultra low standby power
• Easy memory expansion with CE
, CE2, and OE features
1
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
Functional Description
[1]
The CY62167DV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. Placing the device into standby mode reduces power
Logic Block Diagram
consumption by more than 99% when deselected (CE
or CE
LOW or both BHE and BLE are HIGH). The input and
2
output pins (IO
state when:
• Deselected (CE
• Outputs are disabled (OE
through IO15) are placed in a high impedance
0
HIGH or CE2 LOW)
1
HIGH)
HIGH
1
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)
are disabled (BHE
• Write operation is active (CE
LOW)
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then
data from IO pins (IO
specified on the address pins (A
then data from IO pins (IO
location specified on the address pins (A
To read from the device, take Chip Enables (CE
CE
HIGH) and OE LOW while forcing the WE HIGH. If BLE
2
is LOW, then data from the memory location specified by the
address pins appear on IO
from memory appears on IO
page 9 for a complete description of read and write modes.
, BLE HIGH)
LOW, CE2 HIGH and WE
1
LOW and CE
1
through IO7) is written into the location
0
through A19). If BHE is LOW
0
through IO15) is written into the
8
to IO7. If BHE is LOW, then data
0
to IO15. See the “Truth Table” on
8
through A19).
0
LOW and
1
2
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
A
A
A
A
A
A
6
5
4
3
2
1
0
ROW DECODER
1M × 16
RAM Array
SENSE AMPS
IO
–IO
0
IO8–IO
7
15
COLUMN DECODER
BYTE
BHE
11
A
A12A13A14A
15
16
17
18
19
A
A
A
A
Power Down
Circuit
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
BHE
BLE
CE
CE
2
1
WE
OE
BLE
CE
CE
2
1
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05326 Rev. *C Revised April 25, 2007
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CY62167DV18 MoBL
Product Portfolio
Power Dissipation
V
Product
CC
Min Typ
[2]
Max Typ
Speed
(ns)
Range (V)
CY62167DV18LL 1.65 1.8 1.95 55 1.5 5 15 30 2.5 20
Operating I
CC
(mA)
f = 1MHz f = f
[2]
Max Typ
[2]
max
Max Typ
Standby I
[2]
SB2
Max
®
(µA)
Pin Configuration
[3]
BLE
IO
IO
V
V
CC
IO
IO
A
SS
18
OE
BHE
8
IO
10
9
IO
11
IO
12
IO
13
14
A
15
19
A
8
48-Ball VFBGA
Top Vi e w
41
326
A
0
A
3
A
5
A
17
DNU
A
14
A
12
A
9
5
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
IO
IO
IO
IO
WE
A
CE
2
IO
1
IO
1
V
3
V
4
IO
5
IO
DNU
11
CC
SS
A
2
B
0
C
2
D
E
F
6
G
7
H
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
3. DNU pins must be left floating or tied to V
to ensure proper operation.
SS
CC
= V
CC(typ)
, TA = 25°C.
Document #: 38-05326 Rev. *C Page 2 of 11
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CY62167DV18 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential. –0.2V to V
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
........................... –0.2V to V
CCmax
CCmax
+ 0.2V
+ 0.2V
DC Input Voltage
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Range
Industrial –40°C to +85°C 1.65V to 1.95V
DC Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage IOH = −0.1 mA 1.4 V
Output LOW Voltage IOL = 0.1 mA 0.2 V
Input HIGH Voltage 1.4 VCC + 0.2 V
Input LOW Voltage –0.2 0.4 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
VCC Operating Supply Current f = f
f = 1 MHz 1.5 5
Automatic CE Power down
Current − CMOS Inputs
CE1 > VCC − 0.2V, CE2 < 0.2V,
V
f = f
f = 0 (OE
Automatic CE Power down
Current − CMOS Inputs
CE1 > VCC − 0.2V, CE2 < 0.2V,
V
f = 0, V
= 1/t
MAX
> VCC − 0.2V, VIN < 0.2V,
IN
MAX
RCVCC
(Address and Data Only),
= 1.95V, I
CMOS level
, WE, BHE and BLE)
> VCC − 0.2V or VIN < 0.2V,
IN
=1.95V
CC
[4, 5]
........................–0.2V to V
Ambient
Tempe rature
–1 +1 µA
= 0 mA,
OUT
+ 0.2V
CCmax
[6]
V
CC
55 ns
[2]
Max
UnitMin Typ
15 30 mA
2.5 20 µA
2.5 20 µA
Capacitance
[7]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Notes
4. V
IL(min)
5. V
IH(max)
6. Full device AC operation requires linear V
7. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz, VCC = V
Output Capacitance 8 pF
= –2.0V for pulse durations less than 20 ns.
= VCC + 0.75V for pulse durations less than 20 ns.
ramp from 0 to V
CC
and VCC must be stable at V
CC(min)
CC(typ)
CC(min)
for 500 µs.
6pF
Document #: 38-05326 Rev. *C Page 3 of 11
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CY62167DV18 MoBL
®
Thermal Resistance
[7]
Parameter Description Test Conditions VFBGA Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
55 °C/W
16 °C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
JIG AND
R1
VCC
30 pF
SCOPE
R2
Rise Time = 1 V/ns
Equivalent to: THE VENIN EQUIVALENT
GND
OUTPUT V
Parameters 1.8V Unit
R1 13500 Ω
R2 10800 Ω
R
TH
V
TH
6000 Ω
0.80 V
ALL INPUT PULSES
10%
R
TH
90%
90%
10%
Fall Time = 1 V/ns
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[7]
t
CDR
[8]
t
R
Data Retention Waveform
CE
1
BHE,BLE
Notes
8. Full device operation requires linear V
9. BHE
VCC for Data Retention 1.0 1.95 V
V
Data Retention Current
= 1.0V,
CC
V
> VCC – 0.2V or VIN < 0.2V
IN
CE
> VCC – 0.2V, CE2 < 0.2V,
1
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
[9]
RC
DATA RETENTION MODE
V
or
CC
VCC, min
t
CDR
VDR
>
1.0V
VCC, min
t
R
or
CE
2
ramp from V
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
CC
DR
to V
> 100 µs or stable at V
CC(min)
CC(min)
> 100 µs.
[2]
Max Unit
10 µA
ns
Document #: 38-05326 Rev. *C Page 4 of 11
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CY62167DV18 MoBL
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[13]
Read Cycle Time 55 ns
Address to Data Valid 55 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid 55 ns
OE LOW to Data Valid 25 ns
OE LOW to LOW Z
OE HIGH to High Z
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH and CE2 LOW to High Z
[11]
[11, 12]
[11]
[11, 12]
CE1 LOW and CE2 HIGH to Power up 0 ns
CE1 HIGH and CE2 LOW to Power down 55 ns
BLE/BHE LOW to Data Valid 55 ns
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
[11]
[11, 12]
Write Cycle Time 55 ns
CE1 LOW and CE2 HIGH to Write End 40 ns
Address Setup to Write End 40 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 40 ns
BLE/BHE LOW to Write End 45 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High-
WE HIGH to Low-Z
[11, 12]
[11]
[10]
55 ns
Min Max
Unit
5ns
20 ns
10 ns
20 ns
5ns
20 ns
20 ns
10 ns
Notes
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
of 0 to V
11. At any given temperature and voltage condition, t
given device.
12. t
HZOE
13. The internal write time of the memory is defined by the overlap of WE
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
, and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
, t
CC(typ)
HZCE
, t
HZBE
, and t
transitions are measured when the outputs enter a high impedance state.
HZWE
is less than t
HZCE
, t
LZCE
is less than t
HZBE
, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
/2, input pulse levels
CC(typ)
is less than t
LZWE
for any
Document #: 38-05326 Rev. *C Page 5 of 11
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Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[14, 15]
t
AA
CY62167DV18 MoBL
t
RC
RC
®
Read Cycle 2 (OE Controlled)
ADDRESS
CE
1
CE
2
BHE/BLE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
PU
[15, 16]
t
LZBE
t
LZCE
t
ACE
t
LZOE
t
DBE
t
DOE
50%
t
RC
t
PD
t
HZCE
t
HZBE
t
HZOE
HIGH
DATA VALID
IMPEDANCE
I
CC
50%
I
SB
Notes
14. The device is continuously selected. OE
is HIGH for read cycle.
15. WE
16. Address valid before or similar to CE
, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
, BHE, BLE transition LOW and CE2 transition HIGH.
1
Document #: 38-05326 Rev. *C Page 6 of 11
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Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)
ADDRESS
CE
1
CE
2
[13, 17, 18]
t
SCE
t
WC
CY62167DV18 MoBL
®
t
WE
SA
BHE/BLE
OE
DATA IO
NOTE 19
t
HZOE
Write Cycle 2 (CE1 or CE2 Controlled)
ADDRESS
CE
1
CE
2
WE
[13, 17, 18]
t
SA
t
AW
t
PWE
t
BW
t
SD
t
HA
t
HD
VAL I D DATA
t
WC
t
SCE
t
AW
t
PWE
t
HA
t
BHE/BLE
BW
OE
t
HD
DATA IO
Notes
17. Data IO is high impedance if OE
18. If CE
goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
1
19. During this period, the IOs are in output state. Do not apply input signals.
NOTE 19
= VIH.
t
HZOE
t
SD
VALID DATA
Document #: 38-05326 Rev. *C Page 7 of 11
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Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
BHE
/BLE
[18]
t
t
SCE
BW
CY62167DV18 MoBL
t
WC
®
t
SA
WE
DATA IO
NOTE 19
t
HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
/BLE
BHE
t
SA
WE
[18]
t
AW
t
PWE
t
SD
t
HA
t
HD
VAL I D DATA
t
LZWE
t
WC
t
SCE
t
AW
t
BW
t
PWE
t
HA
t
HD
DATA IO
NOTE 19
t
SD
VAL I D DATA
Document #: 38-05326 Rev. *C Page 8 of 11
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Truth Table
CY62167DV18 MoBL
®
CE
CE
1
WE OE BHE BLE Inputs/Outputs Mode Power
2
H X X X X X High Z Deselect/Power Down Standby (I
X L X X X X High Z Deselect/Power Down Standby (I
X X X X H H High Z Deselect/Power Down Standby (I
L H H L L L Data Out (IO
L H H L H L High Z (IO
Data Out (IO
L H H L L H Data Out (IO8–IO15);
High Z (IO
LHLXLLData In (IO
LHLXHLHigh Z (IO
Data In (IO
LHLXLHData In (IO
High Z (IO
–IO15) Read Active (ICC)
0
–IO15);
8
–IO7)
0
Read Active (I
Read Active (I
–IO7)
0
–IO15) Write Active (ICC)
0
–IO15);
8
–IO7)
0
–IO15);
8
–IO7)
0
Write Active (I
Write Active (I
L H H H L H High Z Output Disabled Active (ICC)
L H H H H L High Z Output Disabled Active (I
L H H H L L High Z Output Disabled Active (I
Ordering Information
CC
CC
CC
CC
CC
CC
SB
SB
SB
)
)
)
)
)
)
)
)
)
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
55 CY62167DV18LL-55BVXI 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free) Industrial
Document #: 38-05326 Rev. *C Page 9 of 11
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Package Diagrams
Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178
CY62167DV18 MoBL
®
0.25 C
9.50±0.10
A
0.55 MAX.
0.26 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
A
B
C
8.00±0.10
SEATING PLANE
0.21±0.05
0.10 C
9.50±0.10
5.25
0.75
2.625
B
0.15(4X)
BOTTOM VIEW
Ø0.05MC
Ø0.25 M C A B
Ø0.30±0.05(48X)
65
1.875
0.75
8.00±0.10
3.75
234
A1 CORNER
1
A
B
C
D
E
F
G
H
51-85178-**
1.00 MAX
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05326 Rev. *C Page 10 of 11
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62167DV18 MoBL
Document History Page
Document Title: CY62167DV18 MoBL®, 16-Mbit (1M x 16) Static RAM
Document Number: 38-05326
REV. ECN NO. Issue Date
** 118406 09/30/02 GUG New Data Sheet
*A 123690 02/11/03 DPM Changed Advance to Preliminary
*B 126554 04/25/03 DPM Minor Change: Changed sunset owner from DPM to HRT
*C 1015643 See ECN VKN Converted from preliminary to final
Orig. of
Change
Description of Change
Added package diagram
Removed “L” parts
Removed 70 ns speed bin
Updated footnote #3
Updated Ordering Information table
®
Document #: 38-05326 Rev. *C Page 11 of 11
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