CY62158EV30 MoBL
®
8-Mbit (1024K x 8) Static RAM
Features
• Very high speed: 45 ns
— Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62158DV30
• Ultra low standby power
— Typical standby current: 2 µA
— Maximum standby current: 8 µA
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power down when deselected
• CMOS for optimum speed/power
• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and
48-pin TSOP I packages
[1]
Logic Block Diagram
Functional Description
[2]
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Placing the device into standby
mode reduces power consumption significantly when
deselected (CE
output pins (IO
state when the device is deselected (CE
the outputs are disabled (OE
progress (CE
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. Data on the eight
IO pins (IO
specified on the address pins (A
To read from the device, take Chip Enables (CE
CE
HIGH) and OE LOW while forcing the WE HIGH. Under
2
these conditions, the contents of the memory location
HIGH or CE2 LOW). The eight input and
1
through IO7) are placed in a high impedance
0
HIGH), or a write operation is in
LOW and CE2 HIGH and WE LOW).
1
through IO7) is then written into the location
0
through A19).
0
HIGH or CE2 LOW),
1
LOW and CE
1
LOW and
1
specified by the address pins appear on the IO pins. See the
“Truth Table” on page 8 for a complete description of read and
write modes.
2
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
9
10
11
12
ROW DECODER
A
A
A
CE
1
CE
2
Notes
1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
A
WE
OE
DATA IN DRIVERS
1024K x 8
ARRAY
COLUMN DECODER
14
16
13
A
A
A15A
17
A18A
A
SENSE AMPS
POWER
DOWN
19
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05578 Rev. *D Revised April 19, 2007
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CY62158EV30 MoBL
®
Pin Configurations
1
NC
NCNCNC
IO
0
V
SS
V
CC
IO
3
NC
A
18
[3]
48-Ball VFBGA
Top View
2
3
A
OE
IO
NC
NC
IO
NC
A
0
A
3
A
5
A
17
1
NC
2
A
14
A
12
A
9
8
44-Pin TSOPII
CE
NC
NC
IO
IO
V
V
IO
IO
NC
NC
WE
A
A
A
A
A
A
A
A
A
A
CC
SS
19
18
17
16
15
4
3
2
1
0
1
0
1
2
3
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
A
5
43
A
6
42
A
7
41
OE
40
CE
2
39
A8
38
NC
37
NC
36
IO
7
35
IO
6
34
V
SS
33
V
CC
32
IO
5
31
IO
4
30
NC
29
NC
A
28
9
27
A
10
26
A
11
25
A
12
A
24
13
23
A
14
4
5
6
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
NC
IO
IO
WE
A
CE
2
NC
1
IO
V
5
V
6
IO
NC
A
11
CC
SS
19
A
2
B
C
4
D
E
F
7
G
H
Product Portfolio
Power Dissipation
V
Product
Range (V)
CC
Min Typ
[4]
Max Typ
Speed
(ns)
Operating I
f = 1 MHz f = f
[4]
Max Typ
CY62158EV30LL 2.2 3.0 3.6 45 1.8 3 18 25 2 8
CC
(mA)
[4]
max
Max Typ
Standby, I
[4]
SB2
(µA)
Max
Notes
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
Document #: 38-05578 Rev. *D Page 2 of 11
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CY62158EV30 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Latch up Current......................................................>200 mA
Operating Range
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential–0.3V to V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
[5, 6]
.........................–0.3V to V
[5, 6]
..................... –0.3V to V
CC(max)
CC(max)
CC(max)
+ 0.3V
+ 0.3V
+ 0.3V
CY62158EV30LL Industrial –40°C to +85°C 2.2V – 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IIL
[8]
Output HIGH Voltage IOH = –0.1 mA 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 V
CC
Output LOW Voltage IOL = 0.1 mA 0.4 V
= 2.1 mA, V
I
OL
Input HIGH Voltage V
Input LOW Voltage V
= 2.2V to 2.7V 1.8 V
CC
= 2.7V to 3.6V 2.2 V
V
CC
= 2.2V to 2.7V –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
Input Leakage Current GND < VI < V
> 2.70V 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
VCC Operating Supply Current f = f
Automatic CE
Power down Current —
CMOS Inputs
Automatic CE
Power down Current —
CMOS Inputs
= 1/t
max
f = 1 MHz 1.8 3 mA
CE
> V
1
V
> VCC – 0.2V, VIN < 0.2V)
IN
f = f
max
f = 0 (OE
CE
> VCC – 0.2V or CE2 < 0.2V,
1
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, V
RCVCC
I
OUT
CMOS levels
– 0.2V, CE2 < 0.2V
CC
(Address and Data Only),
and WE), VCC = 3.60V
= 3.60V
CC
Product Range
= V
CCmax
= 0 mA
Ambient
Temperature
45 ns
Min Typ
(TA)
[4]
CC
CC
V
CC
Max
+ 0.3V V
+ 0.3V V
Unit
–1 +1 µA
18 25 mA
28µA
28µA
[7]
Capacitance
[9]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Notes
5. V
6. V
7. Full device AC operation assumes a 100 µs ramp time from 0 to V
8. Only chip enables (CE
9. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min)
= V
IH(max)
+ 0.75V for pulse duration less than 20 ns.
CC
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
SB2
CC(typ)
/ I
spec. Other inputs can be left floating.
CCDR
stabilization.
CC
Output Capacitance 10 pF
(min) and 200 µs wait time after V
and CE2) must be at CMOS level to meet the I
1
CC
10 pF
Document #: 38-05578 Rev. *D Page 3 of 11
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CY62158EV30 MoBL
®
Thermal Resistance
[9]
Parameter Description Test Conditions BGA TSOP II Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
72 76.88 °C/W
8.86 13.52 °C/W
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
INCLUDING
30 pF
JIG AND
SCOPE
R2
VCC
GND
Rise Time: 1 V/ns
Equivalent to:
OUTPUT
10%
Parameters 2.5V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
ALL INPUT PULSES
90%
VENIN EQUIVALENT
THÉ
R
TH
90%
10%
Fall time: 1 V/ns
V
TH
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[10]
t
R
[8]
[9]
VCC for Data Retention 1.5 V
Data Retention Current VCC = 1.5V, CE1 > VCC − 0.2V
or CE
< 0.2V, VIN > VCC − 0.2V
2
< 0.2V
or V
IN
Chip Deselect to Data
0ns
Retention Time
Operation Recovery
Time
t
RC
Data Retention Waveform
DATA RETENTION MODE
V
CE
or
CE
CC
VCC, min
t
CDR
1
2
VDR
>
1.5V
[4]
Max Unit
25µA
VCC, min
t
R
ns
Note
10. Full Device AC operation requires linear V
ramp from V
CC
DR
to V
> 100 µs or stable at V
CC(min)
CC(min)
> 100 µs.
Document #: 38-05578 Rev. *D Page 4 of 11
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CY62158EV30 MoBL
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[14]
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid 45 ns
OE LOW to Data Valid 22 ns
OE LOW to Low Z
OE HIGH to High Z
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH or CE2 LOW to High Z
[12]
[12, 13]
[12]
[12, 13]
CE1 LOW and CE2 HIGH to Power Up 0 ns
CE1 HIGH or CE2 LOW to Power Down 45 ns
Write Cycle Time 45 ns
CE1 LOW and CE2 HIGH to Write End 35 ns
Address Setup to Write End 35 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 35 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High Z
WE HIGH to Low Z
[12, 13]
[12]
[11]
45 ns
Min Max
Unit
5ns
18 ns
10 ns
18 ns
18 ns
10 ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V
pulse levels of 0 to V
12. At any given temperature and voltage condition, t
, t
13. t
HZOE
14. The internal write time of the memory is defined by the overlap of WE
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
HZCE
, and t
, and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
CC(typ)
transitions are measured when the outputs enter a high impedance state.
HZWE
is less than t
HZCE
, t
LZCE
, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
is less than t
HZOE
LZOE
, and t
is less than t
HZWE
for any given device.
LZWE
CC(typ)
/2, input
Document #: 38-05578 Rev. *D Page 5 of 11
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Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
[15, 16]
t
AA
CY62158EV30 MoBL
t
RC
®
DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
1
CE
2
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[16, 17]
t
ACE
t
LZOE
t
DOE
50%
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
I
CC
50%
I
SB
Notes
15. Device is continuously selected. OE
16. WE
is HIGH for read cycle.
17. Address valid before or similar to CE
, CE1 = VIL, CE2 = VIH.
transition LOW and CE2 transition HIGH.
1
Document #: 38-05578 Rev. *D Page 6 of 11
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Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
ADDRESS
CE
1
CE
2
[14, 18, 19]
t
SCE
t
WC
CY62158EV30 MoBL
®
t
SA
WE
OE
DATA IO
NOTE 20
t
HZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)
ADDRESS
CE
1
t
CE
2
SA
[14, 18, 19]
t
AW
t
PWE
t
SD
t
HA
t
HD
VALID DATA
t
WC
t
SCE
t
AW
t
PWE
t
HA
WE
OE
t
HD
DATA IO
Notes
18. Data IO is high impedance if OE
goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
19. If CE
1
20. During this period, the IOs are in output state. Do not apply input signals.
= VIH.
t
SD
VALID DATA
Document #: 38-05578 Rev. *D Page 7 of 11
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Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
[19]
t
SCE
t
WC
CY62158EV30 MoBL
®
t
HA
t
LZWE
t
HD
WE
DATA IO
t
NOTE 20
SA
t
HZWE
t
AW
t
PWE
t
SD
VALID DATA
Truth Table
CE
H X X X High Z Deselect/Power Down Standby (ISB)
X L X X High Z Deselect/Power Down Standby (ISB)
L H H L Data Out Read Active (ICC)
L H H H High Z Output Disabled Active (ICC)
L H L X Data in Write Active (ICC)
CE
1
WE OE Inputs/Outputs Mode Power
2
Ordering Information
Speed
(ns)
Ordering Code
45 CY62158EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial
CY62158EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
Package
Diagram
Package Type
Operating
Range
Document #: 38-05578 Rev. *D Page 8 of 11
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Package Diagrams
Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
CY62158EV30 MoBL
®
0.25 C
8.00±0.10
A
0.55 MAX.
0.26 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
A
B
SEATING PLANE
C
6.00±0.10
0.21±0.05
0.10 C
0.75
5.25
8.00±0.10
2.625
B
0.15(4X)
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
65
1.875
0.75
6.00±0.10
3.75
A1 CORNER
234
1
A
B
C
D
E
F
G
H
51-85150-*D
1.00 MAX
Document #: 38-05578 Rev. *D Page 9 of 11
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Package Diagrams (continued)
Figure 2. 44-Pin TSOP II, 51-85087
CY62158EV30 MoBL
®
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05578 Rev. *D Page 10 of 11
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62158EV30 MoBL
Document History Page
Document Title: CY62158EV30 MoBL®, 8-Mbit (1024K x 8) Static RAM
Document Number: 38-05578
REV. ECN NO. Issue Date
** 270329 See ECN PCI New Data Sheet
*A 291271 See ECN SYT Converted from Advance Information to Preliminary
*B 444306 See ECN NXR Converted from Preliminary to Final.
*C 467052 See ECN NXR Included 44 pin TSOP II package in Product Offering.
*D 1015643 See ECN VKN Added footnote #8 related to I
Orig. of
Change
Description of Change
Changed I
from 4 to 4.5 µA
CCDR
Removed 35 ns speed bin
Removed “L” bin.
Removed 44 pin TSOP II package
Included 48 pin TSOP I package
Changed the I
mA to 25 mA for test condition f = fax = 1/t
Changed the I
Changed the I
0.9 µA to 2 µA respectively.
Typ value from 16 mA to 18 mA and I
CC
max value from 2.3 mA to 3 mA for test condition f = 1MHz.
CC
SB1
and I
max value from 4.5 µA to 8 µA and Typ value from
SB2
RC.
Updated Thermal Resistance table
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for I
Changed the I
Corrected t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Updated the ordering Information and replaced the Package Name column with
in Data Retention Characteristics from 100 µs to t
R
LZOE
LZCE
HZCE
PWE
from 22 to 25
SD
LZWE
CCDR .
max value from 4.5 µA to 5 µA
CCDR
from 3 to 5
from 6 to 10
from 22 to 18
from 30 to 35
from 6 to 10
Package Diagram.
Removed TSOP I package; Added reference to CY62157EV30 TSOP I
Updated the ordering Information table
and I
SB2
CCDR
max value from 28
CC
ns
RC
®
Document #: 38-05578 Rev. *D Page 11 of 11
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