Cypress CY62157EV30 User Manual

CY62157EV30 MoBL

®

8-Mbit (512K x 16) Static RAM

Features

• TSOP I package configurable as 512K x 16 or as 1M x 8 SRAM

• High speed: 45 ns

• Wide voltage range: 2.20V–3.60V

• Pin compatible with CY62157DV30

• Ultra low standby power — Typical Standby current: 2 µA — Maximum Standby current: 8 µA (Industrial)

• Ultra low active power — Typical active current: 1.8 mA @ f = 1 MHz

• Easy memory expansion with CE

, CE2, and OE features

1

• Automatic power down when deselected

• CMOS for optimum speed and power

• Available in both Pb-free and non Pb-free 48-ball VFBGA, Pb-free 44-pin TSOP II and 48-pin TSOP I packages

Functional Description

[1]

The CY62157EV30 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL

®

) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly

Logic Block Diagram

reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE HIGH or CE2 LOW or both BHE and BLE are HIGH). The input or output pins (IO impedance state when:

through IO15) are placed in a high

0

• Deselected (CE1HIGH or CE2 LOW)

• Outputs are disabled (OE HIGH)

• Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH)

• Write operation is active (CE1 LOW, CE2 HIGH and WE LOW)

To write to the device, take Chip Enable (CE HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE

) is LOW, then data from IO pins (IO0 through IO7) is

LOW and CE

1

written into the location specified on the address pins (A through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO specified on the address pins (A

through IO15) is written into the location

8

through A18).

0

To read from the device, take Chip Enable (CE1 LOW and CE HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE

) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO

Table” on page 10 for a complete description of read and write

to IO15. See the “Truth

8

modes.

1

2

0

2

DATA IN DRIVERS

A

10

A

9

A

8

A

7

A A A A A A

A

6 5 4 3 2 1

0

ROW DECODER

512K × 16 / 1M x 8

RAM Array

SENSE AMPS

–IO

IO

0

IO8–IO

7

15

COLUMN DECODER

CE

2

CE

Power Down

Circuit

Notes

1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.

1

BHE

BLE

11

A

A12A13A14A

15

16

17

18

A

BYTE

BHE WE

OE

BLE

CE

2

1

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05445 Rev. *E Revised May 07, 2007

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CY62157EV30 MoBL

Product Portfolio

Power Dissipation

V

Range (V)

Product Range

CC

Min Typ

[2]

Max Typ

CY62157EV30LL Ind’l/Auto-A 2.2V 3.0 3.6 45 1.8 3 18 25 2 8

Pin Configuration

The following pictures show the 44-pin TSOP II and 48-pin TSOP I pinouts.

Speed

(ns)

Operating ICC, (mA)

f = 1MHz f = f

[2]

Max Typ

[3, 4, 5]

max

[2]

Standby, I

Max Typ

(µA)

[2]

SB2

Max

®

44-Pin TSOP II

A

4

A

3

A

2

A

1

A

0

CE

IO

0

IO

1

IO

2

IO

10

3

V

11

CC

V

12

SS

IO

13

4

IO

14

5

IO

15

6

IO

16

7

WE

17

A

18

A

19

17

A

20

16

A

21

15

A

22

14

Top View

1 2 3 4 5 6 7 8 9

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

A

5

A

6

A

7

OE BHE

BLE IO

15

IO

14

IO

13

IO

12

V

SS

V

CC

IO

11

IO

10

IO

9

IO

8

A

8

A

9

A

10

A

11

A

12

A

13

A15 A14 A13 A12 A11 A10 A9 A8 NC DNU WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1

48-Pin TSOP I (512K x 16 / 1M x 8)

Top V iew

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48

A16

47

BYTE

46

Vss

45

IO15/A19

44

IO7

43

IO14

42

IO6

41

IO13

40

IO5

39

IO12

38

IO4

37

Vcc

36

IO11

35

IO3

34

IO10

33

IO2

32

IO9

31

IO1

30

IO8

29

IO0

28

OE

27

Vss

26

CE1

25

A0

Notes

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V

3. NC pins are not connected on the die.

4. The 44-TSOP II package has only one chip enable (CE

5. The BYTE SRAM by tying the BYTE

pin in the 48-TSOP I package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8

signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and IO8 to IO14 pins are not used (DNU).

) pin.

CC

= V

CC(typ)

, TA = 25°C.

Document #: 38-05445 Rev. *E Page 2 of 14

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Pin Configuration (continued)

The following picture shows the 48-ball VFBGA pinout.

1

2

OE

BLE

IO

BHE

8

[3, 4, 5]

48-Ball VFBGA

Top V iew

3

4

A

1

0

A

3

4

A

CE

CY62157EV30 MoBL

5

6

CE

2

IO

1

A

2

B

0

®

IO

V

A

SS

CC

A

9

IO

14

NC

15

18

5

10

A

11

17

NC

12

A

13

14

A

12

A

8

9

A

IO

6

1

IO

WE

A

V

3

V

4

5

11

A

7

A

16

A

15

A

13

A

10

IO

CC

IO

NC

SS

C

2

D

E

F

6

G

7

H

Document #: 38-05445 Rev. *E Page 3 of 14

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®

Maximum Ratings

Exceeding maximum ratings may shorten the battery life of the device. User guidelines are not tested.

Storage Temperature ................................–65°C to + 150°C

Ambient Temperature with

Power Applied ...........................................–55°C to + 125°C

DC Input Voltage

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage .......................................... > 2001V

(MIL-STD-883, Method 3015)

Latch up Current ....................................................> 200 mA

Operating Range

Supply Voltage to Ground

Potential ................................–0.3V to 3.9V (V

DC Voltage Applied to Outputs in High-Z State

[6, 7]

................–0.3V to 3.9V (V

CCmax

+ 0.3V)

Device Range

CY62157EV30LL Ind’l/Auto-A –40°C to +85 °C 2.20V to

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB1

[9]

I

SB2

Capacitance

Output HIGH Voltage IOH = –0.1 mA 2.0 V

= –1.0 mA, V

I

OH

> 2.70V 2.4 V

CC

Output LOW Voltage IOL = 0.1 mA 0.4 V

= 2.1mA, V

I

OL

Input HIGH Voltage V

Input LOW Voltage V

= 2.2V to 2.7V 1.8 V

CC

= 2.7V to 3.6V 2.2 V

V

CC

= 2.2V to 2.7V –0.3 0.6 V

CC

= 2.7V to 3.6V –0.3 0.8 V

V

CC

Input Leakage Current GND < VI < V

> 2.70V 0.4 V

CC

Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA V

Operating Supply Current f = f

CC

= 1/t

max

RC

f = 1 MHz 1.8 3

VCC = V I

= 0 mA

OUT

CMOS levels

Automatic CE Power Down Current — CMOS Inputs

[10]

> V

CE

1

V

>

IN

f = f

max

f = 0 (OE CE

1

V

> VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V

IN

− 0.2V, CE2 < 0.2V

CC

V

– 0.2V, V

CC

< 0.2V)

IN

(Address and Data Only),

, BHE, BLE and WE), V

> VCC – 0.2V or CE2 < 0.2V,

CCmax

CC

[6, 7]

= 3.60V

........... –0.3V to 3.9V (V

Ambient

Temperature

45 ns (Ind’l/Auto-A)

Min Typ

[2]

–1 +1 µA

18 25

28µA

CC max

V

Max

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3V)

CC

3.60V

[8]

Unit

mA

Parameter Description Test Conditions Max Unit

C

IN

C

OUT

Notes

6. V

7. V

8. Full device AC operation assumes a 100 µs ramp time from 0 to V

9. Only chip enables (CE

10. Tested initially and after any design or process changes that may affect these parameters.

= –2.0V for pulse durations less than 20 ns.

IL(min)

= V

IH(max)

inputs can be left floating.

Input Capacitance TA = 25°C, f = 1 MHz,

V

= V

CC

Output Capacitance 10 pF

+ 0.75V for pulse durations less than 20 ns.

CC

and CE2), byte enables (BHE and BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the I

1

CC(typ)

(min) and 200 µs wait time after V

cc

stabilization.

CC

10 pF

SB2

/ I

CCDR

spec. Other

Document #: 38-05445 Rev. *E Page 4 of 14

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CY62157EV30 MoBL

®

Thermal Resistance

[10]

Parameter Description Test Conditions BGA TSOP I TSOP II Unit

Θ

JA

Θ

JC

Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Case)

Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board

72 74.88 76.88 °C/W

8.86 8.6 13.52 °C/W

AC Test Loads and Waveforms

Figure 1. AC Test Loads and Waveforms

R1

V

CC

OUTPUT

30 pF

Rise Time = 1 V/ns

R2

VCC

GND

10%

INCLUDING

JIG AND

Equivalent to: THÉ VENIN EQUIVALENT

SCOPE

Parameters 2.5V 3.0V Unit

R1 16667 1103 Ω R2 15385 1554 Ω

R

TH

V

TH

8000 645 Ω

1.20 1.75 V

ALL INPUT PULSES

90%

10%

Fall Time = 1 V/ns

R

TH

OUTPUT V

TH

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions Min Typ

V

DR

I

CCDR

t

CDR

[11]

t

R

Data Retention Waveform

BHE.BLE

VCC for Data Retention 1.5 V

[9]

Data Retention Current

= 1.5V, CE1 > VCC – 0.2V,

V

CC

Ind’l/Auto-A 2 5 µA

CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V

[10]

Chip Deselect to Data

0ns

Retention Time Operation Recovery Time t

[12]

RC

Figure 2. Data Retention Waveform

DATA RETENTION MODE

V

CC

CE1 or

CE

V

CC(min)

t

CDR

or

2

VDR

>

1.5V

V

CC(min)

t

R

[2]

Max Unit

ns

Notes

11. Full device operation requires linear V

12. BHE

.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.

ramp from V

CC

DR

to V

> 100 µs or stable at V

CC(min)

> 100 µs.

Document #: 38-05445 Rev. *E Page 5 of 14

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Cypress CY62157EV30 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual