CY62157EV18 MoBL
®
8-Mbit (512K x 16) Static RAM
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–2.25V
• Pin Compatible with CY62157DV18 and CY62157DV20
• Ultra low standby power
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
Functional Description
The CY62157EV18 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
, CE2 and OE features
1
[1]
®
) in
deselected (CE
HIGH). The input and output pins (IO
HIGH or CE2 LOW or both BHE and BLE are
1
through IO15) are
0
placed in a high impedance state when:
• Deselected (CE1 HIGH or CE2 LOW)
• Outputs are disabled (OE
HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
• Write operation is active (CE
LOW, CE2 HIGH and WE
1
LOW).
Write to the device by taking Chip Enables (CE
LOW and CE
1
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE
) is LOW, then data from IO pins (IO0 through IO7), is
written into the location specified on the address pins (A
through A18). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO8 through IO15) is written into the location
specified on the address pins (A
Read from the device by taking Chip Enables (CE
CE
HIGH) and Output Enable (OE) LOW while forcing the
2
through A18).
0
LOW and
1
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appear on IO
then data from memory appears on IO
to IO7. If Byte High Enable (BHE) is LOW,
0
to IO15. See the “Truth
8
Table” on page 9 for a complete description of read and write
modes.
2
0
Product Portfolio
Power Dissipation
Product
Range (V)
V
CC
Speed
(ns)
Operating I
f = 1MHz
Min
Typ
[2]
Max
Typ
[2]
Max
CY62157EV18 1.65 1.8 2.25 55 1.8 3 18 25 2 8
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” located at http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05490 Rev. *D Revised March 30, 2007
CC
Typ
, (mA)
f = f
[2]
CC
= V
max
Max
CC(typ)
Standby, I
Typ
, TA = 25°C.
(µA)
SB2
[2]
Max
[+] Feedback
Logic Block Diagram
POWER DOWN
CIRCUIT
CY62157EV18 MoBL
®
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
512K x 16
RAM Array
IO
–IO
0
7
SENSE AMPS
IO8–IO
15
COLUMN DECODER
BHE
11A12A13
A
14
A
BHE
BLE
15
A
18
16
17
A
A
A
CE
2
CE
1
WE
OE
BLE
CE
CE
2
1
Pin Configuration
[3]
48-ball VFBGA
Top View
41
BLE
IO
IO
V
SS
V
CC
IO
IO
A
326
A
OE
BHE
8
IO
9
IO
IO
IO
14
NC
15
18
0
A
3
A
5
10
A
11
17
NC
12
A
14
13
A
12
A
A
9
8
5
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
IO
IO
IO
IO
WE
A
CE
2
IO
1
IO
1
V
3
V
4
IO
5
IO
NC
11
CC
SS
A
2
B
0
C
2
D
E
F
6
G
7
H
Note
3. NC pins are not connected on the die.
Document #: 38-05490 Rev. *D Page 2 of 12
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CY62157EV18 MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential...............................–0.2V to 2.45V (V
CCmax
+ 0.2V)
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(in accordance with MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
..............–0.2V to 2.45V (V
CCmax
+ 0.2V)
CY62157EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[7]
Output HIGH Voltage IOH = –0.1 mA V
Output LOW Voltage IOL = 0.1 mA V
Input HIGH Voltage V
Input LOW Voltage V
Input Leakage
= 1.65V to 2.25V 1.4 V
CC
= 1.65V to 2.25V –0.2 0.4 V
CC
GND < VI < V
CC
Current
Output Leakage
GND < VO < VCC, Output Disabled –1 +1 µA
Current
VCC Operating Supply
Current
Automatic CEPower Down
Current–CMOS Inputs
Automatic CE Power Down
Current–CMOS Inputs
f = f
= 1/t
max
RC
f = 1 MHz 1.8 3 mA
CE1 > VCC−0.2V or CE2 < 0.2V
> V
V
IN
f = f
max
f = 0 (OE
– 0.2V, V
CC
(Address and Data Only),
, WE, BHE and BLE),
< 0.2V)
IN
CE1 > VCC – 0.2V or CE2 < 0.2V,
> VCC – 0.2V or VIN < 0.2V,
V
IN
f = 0, V
CC
= V
CC(max)
.
[4, 5]
......... –0.2V to 2.45V (V
Device Range
Ambient
Tem per atu re
55 ns
Min
= 1.65V 1.4 V
CC
= 1.65V 0.2 V
CC
Typ
[2]
Max
CC
–1 +1 µA
VCC = V
I
= 0 mA
OUT
CC(max)
18 25 mA
CMOS levels
28µA
= V
V
CC
CC(max)
.
28µA
+ 0.2V)
CCmax
[6]
V
CC
Unit
+ 0.2V V
Capacitance
[8]
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = V
CC(typ)
10 pF
Output Capacitance 10 pF
Notes
4. V
5. V
6. Full Device AC operation assumes a 100 µs ramp time from 0 to V
7. Only chip enable (CE
8. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min)
= VCC + 0.5V for pulse durations less than 20 ns.
IH(max)
) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
(min) and 200 µs wait time after VCC stabilization.
CC
spec. Other inputs can be left floating.
SB2
Document #: 38-05490 Rev. *D Page 3 of 12
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CY62157EV18 MoBL
®
Thermal Resistance
[8]
Parameter Description Test Conditions BGA Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
72 °C/W
8.86 °C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
R1
3V
10%
30 pF
R2
Rise Time = 1 V/ns
GND
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT V
Parameters Value Unit
R1 13500 Ω
R2 10800 Ω
R
TH
V
TH
6000 Ω
0.80 V
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min
V
DR
I
CCDR
[8]
t
CDR
[9]
t
R
Data Retention Waveform
BHE.BLE
Notes
9. Full device operation requires linear V
10. BHE
VCC for Data Retention 1.0 V
Data Retention Current VCC= VDR, CE1 > VCC – 0.2V,
< 0.2V,VIN > VCC – 0.2V or VIN < 0.2V
CE
2
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
[10]
DATA RETENTION MODE
V
V
CC
CE1 or
or
CE
2
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
CC
CC(min)
t
CDR
ramp from V
DR
to V
> 100 µs or stable at V
CC(min)
VDR
>
1.0V
CC(min)
> 100 µs.
V
CC(min)
[2]
Typ
Max Unit
13µA
RC
t
R
ns
Document #: 38-05490 Rev. *D Page 4 of 12
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CY62157EV18 MoBL
r
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
[15]
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[16]
Read Cycle Time 55 ns
Address to Data Valid 55 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid 55 ns
OE LOW to Data Valid 25 ns
OE LOW to Low-Z
OE HIGH to High-Z
CE1 LOW and CE2 HIGH to Low-Z
CE1 HIGH and CE2 LOW to High-Z
[13]
[13, 14]
[13]
[13, 14]
CE1 LOW and CE2 HIGH to Power Up 0 ns
CE1 HIGH and CE2 LOW to Power Down 55 ns
BLE/BHE LOW to Data Valid 55 ns
BLE/BHE LOW to Low-Z
BLE/BHE HIGH to High-Z
[13]
[13, 14]
Write Cycle Time 45 ns
CE1 LOW and CE2 HIGH to Write End 35 ns
Address Setup to Write End 35 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 35 ns
BLE/BHE LOW to Write End 35 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[13, 14]
[13]
[11, 12]
55 ns
Unit
Min Max
5ns
18 ns
10 ns
18 ns
10 ns
18 ns
18
ns
10 ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
levels of 0 to V
12. AC timing parameters are subject to byte enable signals (BHE
clarification.
13. At any given temperature and voltage condition, t
given device.
, t
14. t
HZOE
15. If both byte enables are toggled together, this value is 10 ns.
16. The internal write time of the memory is defined by the overlap of WE
HZCE
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
, t
CC(typ)
HZBE
, and t
HZCE
transitions are measured when the output enters a high impedance state.
HZWE
or BLE) not switching when chip is disabled. Please see application note AN13842 for furthe
is less than t
, t
LZCE
is less than t
HZBE
, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
CC(typ)
/2, input pulse
for any
LZWE
Document #: 38-05490 Rev. *D Page 5 of 12
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Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[17, 18]
t
AA
t
RC
RC
CY62157EV18 MoBL
®
Read Cycle 2 (OE Controlled)
ADDRESS
CE
1
CE
2
BHE/BLE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
PU
[18, 19]
t
LZBE
t
LZCE
t
ACE
t
LZOE
t
DBE
t
DOE
50%
t
RC
t
PD
t
HZCE
t
HZBE
t
HZOE
HIGH
DATA VALID
IMPEDANCE
I
CC
50%
I
SB
Notes:
17. The device is continuously selected. OE
18. WE
is HIGH for read cycle.
19. Address valid before or similar to CE
, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
, BHE, BLE transition LOW and CE2 transition HIGH.
1
Document #: 38-05490 Rev. *D Page 6 of 12
[+] Feedback
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)
ADDRESS
CE
1
CE
2
[16, 20, 21]
t
SCE
t
WC
CY62157EV18 MoBL
®
t
WE
SA
BHE/BLE
OE
DATA IO
NOTE 22
t
HZOE
Write Cycle 2 (CE1 or CE2 Controlled)
ADDRESS
CE
1
CE
2
WE
[16, 20, 21]
t
SA
t
AW
t
PWE
t
BW
t
SD
t
HA
t
HD
VAL I D D ATA
t
WC
t
SCE
t
AW
t
PWE
t
HA
t
BHE/BLE
BW
OE
t
HD
DATA IO
Notes:
20. Data IO is high impedance if OE
21. If CE
goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
1
22. During this period, the IOs are in output state and input signals must not be applied.
NOTE 22
= VIH.
t
HZOE
t
SD
VALID DATA
Document #: 38-05490 Rev. *D Page 7 of 12
[+] Feedback
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
/BLE
BHE
[21]
t
t
SCE
BW
t
WC
CY62157EV18 MoBL
®
t
SA
WE
DATA IO
NOTE 22
t
HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
/BLE
BHE
t
SA
WE
[21]
t
AW
t
PWE
t
SD
t
HA
t
HD
VAL I D D ATA
t
LZWE
t
WC
t
SCE
t
AW
t
BW
t
PWE
t
HA
t
HD
DATA IO
NOTE 22
t
SD
VAL I D D ATA
Document #: 38-05490 Rev. *D Page 8 of 12
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Truth Table
CY62157EV18 MoBL
®
CE
CE
1
WE OE BHE BLE Inputs/Outputs Mode Power
2
H X X X X X High-Z Deselect/Power Down Standby (ISB)
X L X X X X High-Z Deselect/Power Down Standby (I
X X X X H H High-Z Deselect/Power Down Standby (I
L H H L L L Data Out (IO
L H H L H L Data Out (IO0–IO7);
High-Z (IO
L H H L L H High-Z (IO
Data Out (IO
–IO15) Read Active (ICC)
0
Read Active (I
–IO15)
8
–IO7);
0
8
–IO15)
Read Active (I
L H H H L H High-Z Output Disabled Active (I
L H H H H L High-Z Output Disabled Active (ICC)
L H H H L L High-Z Output Disabled Active (ICC)
L H L X L L Data In (IO
L H L X H L Data In (IO
–IO15) Write Active (ICC)
0
–IO7);
0
Write Active (ICC)
High-Z (IO8–IO15)
L H L X L H High-Z (IO
–IO7);
0
Write Active (ICC)
Data In (IO8–IO15)
Ordering Information
Speed
(ns) Ordering Code
55 CY62157EV18LL-55BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial
Contact your local Cypress sales representative for availability of these parts
Package
Diagram
Package Type
Operating
SB
SB
CC
CC
CC
Range
)
)
)
)
)
Document #: 38-05490 Rev. *D Page 9 of 12
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Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW
A1 CORNER
465231
CY62157EV18 MoBL
BOTTOM VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
234
65
1
®
A
B
C
D
E
F
G
H
51-85150-*D
0.25 C
8.00±0.10
A
0.55 MAX.
0.26 MAX.
A
B
C
D
E
F
G
H
B
SEATING PLANE
C
6.00±0.10
0.21±0.05
0.10 C
1.00 MAX
8.00±0.10
A
5.25
0.75
B
0.15(4X)
2.625
1.875
0.75
3.75
6.00±0.10
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05490 Rev. *D Page 10 of 12
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History
Document Title: CY62157EV18 MoBL® 8-Mbit (512K x 16) Static RAM
Document Number:38-05490
REV. ECN NO. Issue Date
** 202862 See ECN AJU New Data Sheet
*A 291272 See ECN SYT Converted from Advance Information to Preliminary
*B 444306 See ECN NXR Converted from Preliminary to Final
*C 571786 See ECN VKN Replaced 45ns speed bin with 55ns
Orig. of
Change
Description of Change
Changed V
Changed V
Changed I
Changed t
Changed t
Max from 2.20 to 2.25 V
CC
stabilization time in footnote #7 from 100 µs to 200 µs
CC
from 4 to 4.5 µA
CCDR
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bins
OHA
from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
DOE
respectively
Changed t
HZOE
HZBE
and t
from 12 and 15 ns to 15 and 18 ns for the 35 and 45
HZWE
, t
ns Speed Bins respectively
Changed t
from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
HZCE
respectively
, t
Changed t
SCE
and tBW from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns
AW,
Speed Bins respectively
Changed t
from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins
SD
respectively
Added Pb-Free Package Information
Removed 35 ns speed bin
Removed “L” bin
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU
Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2.4V to
2.45V
Changed the I
mA for test condition f = fax = 1/t
Changed the I
Changed the I
Typ value from 16 mA to 18 mA and I
CC
RC
Max value from 2.3 mA to 3 mA for test condition f = 1MHz
CC
SB1
and I
Max value from 4.5 µA to 8 µA and Typ value from 0.9 µA
SB2
to 2 µA respectively
Updated Thermal Resistance table
Changed Test Load Capacitance from 50 pF to 30 pF
Added Typ value for I
Changed the I
Corrected t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
in Data Retention Characteristics from 100 µs to t
R
LZOE
LZCE
HZCE
LZBE
PWE
from 22 to 25
SD
LZWE
CCDR
Max value from 4.5 µA to 3 µA
CCDR
from 3 to 5
from 6 to 10
from 22 to 18
from 6 to 5
from 30 to 35
from 6 to 10
Added footnote #13
Updated the ordering Information and replaced the Package Name column with
Package Diagram
CY62157EV18 MoBL
Max value from 28 mA to 25
CC
ns
RC
®
Document #: 38-05490 Rev. *D Page 11 of 12
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CY62157EV18 MoBL
®
Document Title: CY62157EV18 MoBL
Document Number:38-05490
REV. ECN NO. Issue Date
*D 908120 See ECN VKN Added footnote #7 related to I
Orig. of
Change
®
8-Mbit (512K x 16) Static RAM
Added footnote #12 related AC timing parameters
Description of Change
SB2
Document #: 38-05490 Rev. *D Page 12 of 12
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