Cypress CY62148EV30 User Manual
MoBL® CY62148EV30
4-Mbit (512K x 8) Static RAM
Features
Notes
1. SOIC package is available only in 55 ns speed bin.
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A
13
A
14
A
15
A16A
17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A
10
A
11
A
12
A
18
■ Very high speed: 45 ns
❐ Wide voltage range: 2.20V to 3.60V
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
■ Pin compatible with CY62148DV30
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA (Industrial)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin
SOIC
[1]
packages
Logic Block Diagram
Functional Description
The CY62148EV30
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE
HIGH). The eight input and output pins (IO0 through IO7) are
placed in a high impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
To write to the device, take Chip Enable (CE
(WE
) inputs LOW. Data on the eight IO pins (IO0 through IO7) is
then written into the location specified on the address pins (A
through A18).
To read from the device, take Chip Enable (CE
Enable (OE
) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
[2]
is a high performance CMOS static RAM
LOW and WE LOW).
®
) in portable
) and Write Enable
) and Output
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05576 Rev. *G Revised August 4, 2008
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MoBL® CY62148EV30
Pin Configuration
A
15
V
CC
A
13
A
12
A
5
NC
WE
A
7
IO
4
IO
5
A
4
IO
6
IO
7
V
ss
A
11
A
10
A
1
V
SS
IO
0
A
2
A
8
A
6
A
3
A
0
V
cc
IO
1
IO
2
IO
3
A
17
A
18
A
16
CE
OE
A
9
A
14
D
E
B
A
C
F
G
H
NC
36-Ball VFBGA Pinout
Top View
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC/TSOP II Pinout
Top Vi ew
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
V
SS
V
CC
A
18
WE
OE
CE
Notes
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
Product Portfolio
[1, 3]
Power Dissipation
Product Range VCC Range (V)
Min Typ
[4]
Max Typ
Speed
(ns)
Operating ICC (mA)
f = 1 MHz f = f
[4]
Max Typ
[4]
max
Max Typ
Standby I
(µA)
[4]
Max
CY62148EV30LL VFBGA Ind’l 2.2 3.0 3.6 45 2 2.5 15 20 1 7
TSOP II Ind’l/Auto-A
SOIC Ind’l 2.2 3.0 3.6 55 2 2.5 15 20 1 7
SB2
Document #: 38-05576 Rev. *G Page 2 of 12
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MoBL® CY62148EV30
Maximum Ratings
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC(min)
and 200 μs wait time after V
CC
stabilization.
8. Under DC conditions the device meets a V
IL
of 0.8V (for VCC range of 2.7V to 3.6V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic conditions
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to
AN13470 for details.
9. Only chip enable (CE
) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied .............................................. 55°C to +125°C
Supply Voltage to Ground
Potential..........................................–0.3V to V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
........................–0.3V to V
CC(max)
CC(max)
+ 0.3V
+ 0.3V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[9]
Output HIGH
Vol tage
Output LOW
Vol tage
Input HIGH
Vol tage
Input LOW
Vol tage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power Down
Current — CMOS
Inputs
Automatic CE
Power Down
Current — CMOS
Inputs
IOH = –0.1 mA 2.0 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 2.4 V
CC
IOL = 0.1 mA 0.4 0.2 V
IOL = 2.1 mA, V
V
= 2.2V to 2.7V 1.8 V
CC
> 2.70V 0.4 0.4 V
CC
VCC= 2.7V to 3.6V 2.2 V
V
= 2.2V to 2.7V For VFBGA and
CC
TSOP II package
For SOIC package –0.3 0.4
= 2.7V to 3.6V For VFBGA and
V
CC
TSOP II package
For SOIC package –0.3 0.6
GND < VI < V
CC
GND < VO < VCC, Output Disabled –1 +1 –1 +1 μA
f = f
= 1/t
max
f = 1 MHz 2 2.5 2 2.5
CE > V
V
IN
f = f
f = 0 (OE
– 0.2V,
CC
> V
– 0.2V, VIN < 0.2V
CC
(Address and Data Only),
max
and WE), V
RC
VCC = V
I
OUT
CC(max),
= 0 mA,
CMOS levels
= 3.60V
CC
CE > VCC – 0.2V,
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, V
= 3.60V
CC
DC Input Voltage
[5, 6]
.....................–0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Product Range
Ambient
Temperature
CY62148EV30 Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
- 45 (Ind’l/Auto-A) - 55
Min Typ
[4]
Max Min Typ
+ 0.3V 1.8 V
CC
+ 0.3V 2.2 V
CC
[1]
[4]
Max
+ 0.3V V
CC
+ 0.3V V
CC
–0.3 0.6 V
[8]
–0.3 0.8 V
[8]
–1 +1 –1 +1 μA
15 20 15 20 mA
17 17μA
17 17μA
V
Unit
CC
V
[7]
Document #: 38-05576 Rev. *G Page 3 of 12
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MoBL® CY62148EV30
Capacitance (For All packages)
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
CC(min)
V
CC(min)
t
CDR
VDR> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
[10]
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
= V
V
CC
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
[10]
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
VFBGA
Package
TSOP II
Package
SOIC
Package
72 75.13 55 °C/W
8.86 8.95 22 °C/W
Unit
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[11]
t
R
[10]
VCC for Data Retention 1.5 V
[9]
Data Retention Current VCC = 1.5V, CE > VCC – 0.2V,
> VCC – 0.2V or VIN <
V
IN
0.2V
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
Data Retention Waveform
Document #: 38-05576 Rev. *G Page 4 of 12
Ind’l/Auto-A 0.8 7 μA
[4]
Max Unit
RC
ns
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