Cypress CY62148E User Manual
CY62148E MoBL
®
4-Mbit (512K x 8) Static RAM
Features
• Very high speed: 45 ns
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62148B
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA (Industrial)
• Ultra low active power
— Typical active current: 2.0 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin TSOP II and 32-pin SOIC
packages
, and OE features
[2]
Functional Description
[1]
The CY62148E is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
The eight input and output pins (IO
through IO7) are placed
0
HIGH).
in a high impedance state when:
• Deselected (CE
HIGH)
• Outputs are disabled (OE HIGH)
• Write operation is active (CE
To write to the device, take Chip Enable (CE
(WE
) inputs LOW. Data on the eight IO pins (IO0 through IO7)
LOW and WE LOW)
) and Write Enable
is then written into the location specified on the address pins
(A
through A18).
0
To read from the device, take Chip Enable (CE) and Output
Enable (OE
) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
Product Portfolio
Power Dissipation
Product Range VCC Range (V)
Min Typ
[3]
Max Typ
CY62148ELL TSOP II Ind’l 4.5 5.0 5.5 45 2 2.5 15 20 1 7
CY62148ELL SOIC Ind’l/Auto-A 4.5 5.0 5.5 55 2 2.5 15 20 1 7
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
2. SOIC package is available only in 55 ns speed bin.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Speed
(ns)
Operating ICC (mA)
f = 1MHz f = f
[3]
Max Typ
CC
= V
[3]
CC(typ)
Standby I
max
Max Typ
, TA = 25°C.
SB2
[3]
(µA)
Max
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05442 Rev. *F Revised March 28, 2007
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Logic Block Diagram
CE
WE
OE
CY62148E MoBL
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
A
A
A
9
10
11
12
ROW DECODER
INPUT BUFFER
512K x 8
ARRAY
COLUMN DECODER
15
13
14
A
A
A16A
A
SENSE AMPS
POWER
DOWN
17
18
A
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
®
Pin Configuration
[2, 4]
32-pin SOIC/TSOP II Pinout
Top View
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
12
0
IO
13
0
IO
1
14
IO
15
2
V
16
SS
V
CC
32
A
31
15
A
30
18
29
WE
A
28
13
A
8
27
A
26
9
A
25
11
24
OE
A
23
10
22
CE
21
IO
7
IO
20
6
IO
19
5
18
IO
4
17
IO
3
Note
4. NC pins are not connected on the die.
Document #: 38-05442 Rev. *F Page 2 of 10
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CY62148E MoBL
[5, 6]
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
DC Input Voltage
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ......................................................>200mA
Operating Range
Supply Voltage to Ground
Potential.................................–0.5V to 6.0V (V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
................–0.5V to 6.0V (V
CCmax
CCmax
+ 0.5V)
+ 0.5V)
Device Range
CY62148E Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
Output HIGH
Volta ge
Output LOW Voltage IOL = 2.1 mA 0.4 0.4 V
Input HIGH Voltage V
Input LOW voltage V
IOH = –1 mA 2.4 2.4 V
= 4.5V to 5.5V 2.2 V
CC
= 4.5V to 5.5V For TSOPII
CC
package
For SOIC
package
I
IX
I
OZ
I
CC
[9]
I
SB2
Capacitance (For All Packages)
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE Power
down Current —
CMOS Inputs
GND < VI < V
CC
GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA
f = f
= 1/t
max
RC
f = 1 MHz 2 2.5 2 2.5
CE
> VCC – 0.2V
V
> VCC – 0.2V or V
IN
f = 0, V
[10]
CC
= V
CC(max)
VCC = V
I
CMOS levels
OUT
IN
CC(max)
= 0 mA
< 0.2V,
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
= V
V
CC
Output Capacitance 10 pF
CC(typ)
Min Typ
–0.5 0.8 V
–1 +1 –1 +1 µA
............ –0.5V to 6.0V (V
Ambient
Tem per atu re
45 ns 55 ns
[3]
Max Min Typ
+ 0.5 2.2 V
CC
[2]
[3]
–0.5 0.6
15 20 15 20 mA
17 17µA
10 pF
CCmax
Max
+ 0.5 V
CC
[8]
+ 0.5V)
V
CC
®
[7]
Unit
Notes
5. V
6. V
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
8. Under DC conditions the device meets a V
9. Only chip enable (CE
10. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
= VCC+0.75V for pulse durations less than 20 ns.
IH(max)
of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6V. This
is applicable to SOIC package only. Refer to AN13470 for details.
) must be HIGH at CMOS level to meet the I
IL
(min) and 200 µs wait time after V
CC
spec. Other inputs can be left floating.
SB2
stabilization.
CC
Document #: 38-05442 Rev. *F Page 3 of 10
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