Cypress CY62147DV30 User Manual

CY62147DV30

4-Mbit (256K x 16) Static RAM

Features

• Temperature Ranges

— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automot ive-E: –40°C to +125°C

• Very high speed: 45 ns

• Wide voltage range: 2.20V–3.60V

• Pin-compatible with CY62147CV25, CY62147CV30, and
CY62147CV33

• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = f

• Ultra low standby power

• Easy memory expansion with CE

, and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Available in Pb-free and non Pb-free 48-ball VFBGA and
non Pb-free 44-pin TSOPII

• Byte power-down feature

Functional Description

[1]

The CY62147DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-

max

vanced circuit design to provide ultra-low active current. Thi s
is ideal for providing More Battery Life™ (MoBL

®

) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE
input/output pins (I/O
pedance state when: deselected (CE
abled (OE
are disabled (BHE

HIGH or both BLE and BHE are HIGH). The

through I/O15) are placed in a high-im-

0

HIGH), outputs are dis-

HIGH), both Byte High Enable and Byte Low Enable

, BLE HIGH), or during a write operation (CE

LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable

(CE

) and Write Enable (WE) inputs LOW. If Byte Low Enable

) is LOW, then data from I/O pins (I/O0 through I/O7), is

(BLE
written into the location specified on the address pins (A
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A

through I/O15) is written into the location

8

through A17).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE

) and Output Enable (OE) LOW while forcing the

) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete

to I/O15. See

8

description of read and write modes.
The CY62147DV30 is available in a 48-ball VFBGA, 44 Pin

TSOPII packages.

0

Logic Block Diagram

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

Power -Down
Circuit

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

DATA IN DRIVERS

256K x 16

RAM Array

ROW DECODER

COLUMN DECODER

11

A

A12A

I/O

–I/O

0

7

SENSE AMPS

CE

16

15

A

BHE
BLE

17

A

A

14

A

13

I/O8–I/O

15

BHE
WE
CE
OE
BLE

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05340 Rev. *F Revised August 31, 2006

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CY62147DV30

Pin Configuration

1

2

OE

BLE

I/O

BHE

8

I/O

I/O

V

V

I/O

I/O

NC

SS

CC

10

9

I/O

11

I/O

12

I/O

13

14

NC

15

A

8

[2, 3, 4]

VFBGA (Top View) 44 TSOP II (Top View)

4

3

A

0

A

3

A

5

A

17

DNU

A

14

A

12

A

9

5

6

A

A

1

A

4

A

6

A

7

A

16

A

15

A

13

A

10

CE

I/O

I/O

I/O

I/O

WE

A

NC

2

I/O

I/O

1

Vcc

3

Vss

4

I/O

5

I/O

NC

11

A

B

0

C

2

D

E

F

6

G

7

H

I/O
I/O

I/O
I/O

V

V
I/O
I/O
I/O
I/O

WE
A
A

A
A

A

A
A
A
A
A

CE

CC
SS

44

1

4

2

3

3

2

4

1

5

0

6
7

0

8

1

9

2

10

3

11
12
13

4

14

5

15

6

16

7

17
18

17

19

16

20

15

21

14

22

13

A

5

43

A

6

42

A

7

41

OE

40

BHE

39

BLE

38

I/O

37

I/O

36

I/O

35

I/O

34

V

SS

33

V

CC

32

I/O

31

I/O

30

I/O

29

I/O
NC

28
27

A

8

26

A

9

A

25

10

A

24

11

23

A

12

15
14
13
12

11
10
9
8

Product Portfolio

Power Dissipation

CC

CC

= V

(mA)

max

[5]

CC(typ.)

Standby I

Max. Typ.

, TA = 25°C.

(µA)Range f = 1MHz f = f

[5]

Max.

Operating I

[5]

Max. Typ.

Product VCC Range (V)

Min. Typ.

[5]

Speed

(ns)

Max. Typ.

CY62147DV30LL Industrial 2.2V 3.0 3.6 45 1.5 3 10 20 2 8
CY62147DV30LL Industrial 2.2V 3.0 3.6 55 1.5 3 8 15 2 8
CY62147DV30L Auto-E 25
CY62147DV30LL Industrial 2.2V 3.0 3.6 70 1.5 3 8 15 2 8
CY62147DV30LL Auto-A 8

Notes:

2. NC pins are not internally connected on the die.

3. DNU pins have to be left floating or tied to V

4. Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.

5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V

to ensure proper application.

SS

SB2

Document #: 38-05340 Rev. *F Page 2 of 12

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CY62147DV30

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground

Potential......................................–0.3V to + V

DC Voltage Applied to Outputs
in High-Z State

DC Input Voltage

[6,7]

..........................–0.3V to V

[6,7]

..................... –0.3V to V

CC(MAX)

CC(MAX)
CC(MAX)

+ 0.3V

+ 0.3V

+ 0.3V

Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions

V

V

V

V

I

IX

I

OZ

I

CC

I

SB1

I

SB2

OH

OL

IH

IL

Output HIGH
Voltage

Output LOW
Voltage

Input HIGH
Voltage

Input LOW
Voltage

Input Leakage
Current

Output
Leakage
Current

VCC Operating
Supply
Current

Automatic CE
Power-Down
Current —
CMOS Inputs

Automatic CE
Power-Down
Current —
CMOS Inputs

IOH = –0.1 mA V

= –1.0 mA V

I

OH

IOL = 0.1 mA V

= 2.1 mA V

I

OL

V

= 2.2V to 2.7V 1.8 V

CC

= 2.7V to 3.6V 2.2 V

V

CC

V

= 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V

CC

= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V

V

CC

GND < VI < V

CC

= 2.20V 2.0 2.0 V

CC

= 2.70V 2.4 2.4 V

CC

= 2.20V 0.4 0.4 V

CC

= 2.70V 0.4 0.4 V

CC

Ind’l
Auto-A

Auto-E

GND <

VO < VCC,

Output Disabled

Ind’l
Auto-A

Auto-E
f = f
f = 1 MHz 1.5 3 1.5 3 mA

CE
V
f = f
Data Only),
f = 0 (OE
BLE

CE > VCC – 0.2V,
V
V
f = 0, V

= 1/t

MAX

RC

> VCC−0.2V,

–0.2V, VIN<0.2V)

IN>VCC

(Address and

MAX

, WE, BHE and

), V

= 3.60V

CC

> VCC – 0.2V or

IN

< 0.2V,

IN

= 3.60V

CC

V

= V

CC

I

= 0 mA

OUT

CMOS levels

Ind’l LL 8 8 µA

Auto-A

Auto-E

Ind’l LL 8 8 µA

Auto-A

Auto-E

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current......................................................>200 mA

Operating Range

Ambient

Device Range

Temperature

CY62147DV30L Automotive-E –40°C to +125°C 2.20V
CY62147DV30LL Industrial –40°C to +85°C

Automotive-A –40°C to +85°C

–45 –55/–70

[5]

Max. Min. Typ.

+ 0.3V 1.8 V

CC

+ 0.3V 2.2 V

CC

–1 +1 –1 +1 µA

[9]
[9]

–1 +1 µA
–4 +4 µA

–1 +1 –1 +1 µA

[9]
[9]

CCmax

[9]

LL 8

[9]

L25

[9]

LL 8

[9]

L25

10 20 8 15 mA

–1 +1 µA
–4 +4 µA

[TA]

[5]

[9]

CC
CC

3.60V

Max.

+ 0.3V V
+ 0.3V V

V

CC

to

UnitMin. Typ.

Notes:

6. V

7. V

8. Full device AC operation assumes a 100-µs ramp time from 0 to V

9. Auto-A is available in –70 and Auto-E is available in –55.

= –2.0V for pulse durations less than 20 ns.

IL(min.)

= V

IH(max.)

+ 0.75V for pulse durations less than 20 ns.

CC

(min) and 200-µs wait time after V

CC

stabilization.

CC

Document #: 38-05340 Rev. *F Page 3 of 12

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CY62147DV30

Capacitance (for all p ackages)

[10]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Thermal Resistance

Input Capacitance TA = 25°C, f = 1 MHz,

V

= V

CC

Output Capacitance 10 pF

[10]

CC(typ)

10 pF

Parameter Description Test Conditions VFBGA TSOP II Unit

Θ

JA

Θ

JC

AC Test Loads and Waveforms

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

R1

CC

OUTPUT

50 pF

Still Air , soldered on a 3 × 4.5 inch, four-layer
printed circuit board

[10]

Rise Time = 1 V/ns

R2

VCC V

GND

10%

ALL INPUT PULSES

90%

72 75.13 °C/W

8.86 8.95 °C/W

90%

10%

Fall Time = 1 V/ns

INCLUDING

JIG AND

SCOPE

Equivalent to: THÉ VENIN EQUIVALENT

R

TH

OUTPUT V

Parameters 2.50V 3.0V Unit

R1 16667 1103 Ω
R2 15385 1554 Ω

R

TH

V

TH

8000 645 Ω

1.20 1.75 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min. Typ.

V

DR

I

CCDR

[10]

t

CDR

[12]

t

R

Data Retention Waveform

CE or
BHE

VCC for Data Retention 1.5 V
Data Retention Current VCC= 1.5V

CE

> VCC – 0.2V ,

V

> VCC – 0.2V or

IN

V

< 0.2V

IN

Chip Deselect to Data Retention

L (Auto-E) 15 µA

LL (Ind’l/Auto-A) 6

0 ns

Time
Operation Recovery Time t

[13]

DATA RETENTION MODE

VDR> 1.5 V

V

CC

.BLE

V

CC(min)

t

CDR

RC

V

CC(min)

t

R

[5]

Max. Unit

ns

Notes:

10.Tested initially and after any design or process changes that may affect these parameters.

11.Test condition for the 45-ns part is a load capacitance of 30 pF.

12.Full device operation requires linear V

13.BHE

.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

ramp from V

CC

DR

to V

> 100 µs or stab le at V

CC(min.)

CC(min.)

> 100 µs.

Document #: 38-05340 Rev. *F Page 4 of 12

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