CY62147DV18
MoBL2™
4-Mb (256K x 16) Static RAM
Features
• Very high speed: 55 ns and 70 ns
• Wide voltage range: 1.65V – 2.25V
• Pin-compatible with CY62147CV18
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 6 mA @ f = f
max
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA
Functional Description
[1]
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
Logic Block Diagram
mode reducing power consumption by more than 99% when
deselected (
input/output pins (I/O
pedance state when: deselected (CE HIGH), outputs are dis-
CE HIGH or both BLE and BHE are HIGH). The
through I/O15) are placed in a high-im-
0
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (
BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (
I/O
(A
from I/O pins (I/O
specified on the address pins (A
BLE) is LOW, then data from I/O pins (I/O0 through
), is written into the location specified on the address pins
7
through A17). If Byte High Enable (BHE) is LOW, then data
0
through I/O15) is written into the location
8
through A17).
0
Reading from the device is accomplished by asserting Chip
Enable (
Write Enable (
CE) and Output Enable (OE) LOW while forcing the
WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
-
LOW, then data from memory will appear on I/O
the truth table for a complete description of read and write
to I/O7. If Byte High Enable (BHE) is
0
to I/O15. See
8
modes.
The CY62147DV18 is available in a 48-ball FBGA package.
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Power-Down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
DATA IN DRIVERS
ROW DECODER
COLUMN DECODER
11
A
A12A
256K x 16
RAM Array
13
14
A
I/O
– I/O
0
7
SENSE AMPS
16
15
17
A
A
A
I/O8 – I/O
BHE
WE
CE
OE
BLE
15
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05343 Rev. *B Revised February 26, 2004
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CY62147DV18
MoBL2™
Pin Configuration
[2, 3, 4]
FBGA (Top View)
1
2
OE
BLE
I/O
BHE
8
I/O
I/O
V
V
I/O
I/O
NC
Notes:
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating or tied to Vss to ensure proper application.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively.
SS
CC
10
9
I/O
11
DNU
I/O
12
I/O
13
14
NC
15
A
8
4
3
A
0
A
3
A
5
A
17
A
14
A
12
A
9
5
6
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
I/O
I/O
I/O
I/O
WE
A
NC
2
I/O
I/O
1
Vcc
3
Vss
4
I/O
5
I/O
NC
11
A
B
0
C
2
D
E
F
6
G
7
H
Document #: 38-05343 Rev. *B Page 2 of 11
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CY62147DV18
MoBL2™
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground
Potential......................................–0.2V to + V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
[5,6]
..........................–0.2V to V
[5,6]
.....................–0.2V to V
CC(MAX)
CC(MAX)
CC (MAX)
+ 0.2V
+ 0.2V
+ 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Ambient
Device Range
CY62147DV18L Industrial –40°C to +85°C 1.65V to 2.25V
CY62147DV18LL
Temperature
(TA) V
CC
Product Portfolio
Power Dissipation
Operating ICC (mA)
Product
VCC Range (V)
Min. Typ.
[7]
Speed
Max. Typ .
(ns)
[7]
Max. Typ.
max
[7]
Max. Typ.
Standby I
[7]
SB2
Max.
CY62147DV18L 1.65 1.8 2.25 55 1.0 2.0 6 15 0.5 18
CY62147DV18LL 10 12
CY62147DV18L 1.65 1.8 2.25 70 1.0 2.0 6 15 0.5 18
CY62147DV18LL 10 12
Electrical Characteristics Over the Operating Range
CY62147DV18-55 CY62147DV18-70
Parameter Description Test Conditions
V
V
V
V
I
I
I
OH
OL
IH
IL
IX
OZ
CC
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
IOH = –0.1 mA V
IOL = 0.1 mA V
V
=1.65V to 2.25V 1.4 V
CC
V
=1.65V to 2.25V –0.2 0.4 –0.2 0.4 V
CC
GND < VI < V
CC
= 1.65V 1.4 1.4 V
CC
= 1.65V 0.2 0.2 V
CC
GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA
f = f
f = 1 MHz V
MAX
= 1/t
RC
V
CC(max)
I
= 0 mA
OUT
CMOS levels
V
CC(max)
I
= 0 mA
OUT
CMOS levels
CC(max)
–1 +1 –1 +1 µA
= 1.95V
L 6 12 6 12 mA
LL 8 8
= 2.25V
L 6 15 6 15 mA
LL 10 10
= 1.95V L 1 1.5 1 1.5 mA
[7]
Max. Min. Ty p.
+ 0.2V 1.4 V
CC
LL
V
= 2.25V L 1 2 1 2 mA
CC(max)
LL
Notes:
5. V
6. V
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
IH(max)=VCC
+0.75V for pulse durations less than 20ns.
CC(typ.)
[7]
, TA = 25°C.
Max.
+ 0.2V V
CC
[7]
(µA)f = 1MHz f = f
UnitMin. Ty p.
Document #: 38-05343 Rev. *B Page 3 of 11
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CY62147DV18
MoBL2™
Electrical Characteristics Over the Operating Range (continued)
CY62147DV18-55 CY62147DV18-70
[7]
Parameter Description Test Conditions
I
SB1
Automatic CE
Power-Down
Current —
CMOS Inputs
CE > VCC−0.2V,
VIN>VCC–0.2V,
V
<0.2V); f = f
IN
(Address and Data
Only), f = 0 (
MAX
OE,
V
CC(max)
V
CC(max)
WE, BHE and BLE)
I
SB2
Automatic CE
Power-down
Current —
CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC – 0.2V or
V
< 0.2V, f = 0
IN
V
CC(max)
V
CC(max)
=1.95V L 0.5 12 0.5 12 µA
LL 8 8
=2.25V L 0.5 18 0.5 18
LL 12 12
=1.95V L 0.5 12 0.5 12 µA
LL 8 8
=2.25V L 0.5 18 0.5 18
Max. Min. Typ.
LL 12 12
Capacitance for all Packages
[8]
Parameter Description Test Conditions Max. Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
VCC = V
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
Parameter Description Test Conditions BGA Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
[8]
[8]
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
[7]
Max.
75 °C/W
10 °C/W
UnitMin. Typ.
AC Test Loads and Waveforms
R1
CC
OUTPUT
INCLUDING
JIG AND
30 pF
R2
VCC V
GND
10%
Rise Time = 1 V/ns
Equivalent to: THÉ VENIN EQUIVALENT
SCOPE
Parameters 1.80V Unit
R1 13500 Ω
R2 10800 Ω
R
TH
V
TH
6000 Ω
0.80 V
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
R
TH
OUTPUT V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
V
DR
I
CCDR
[8]
t
CDR
t
R
Notes:
8. Tested initially and after any design or process changes that may affect these parameters.
VCC for Data Retention 1.0 V
Data Retention Current VCC= 1.0V CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
L 6 µA
LL 4
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
RC
[7]
Max. Unit
ns
Document #: 38-05343 Rev. *B Page 4 of 11
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CY62147DV18
MoBL2™
wqewqewq
Data Retention Waveform
[9]
DATA RETENTION MODE
V
CC(min)
t
CDR
CE or
BHE
V
CC
.BLE
Switching Characteristics Over the Operating Range
VDR> 1.0 V
[10.]
V
CC(min)
t
R
55 ns 70 ns
Parameter Description
UnitMin. Max. Min. Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signal or by disabling both BHE and BLE.
10. Test conditions for all parameters other than three-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
pulse levels of 0 to V
11. At any given temperature and voltage condition, t
given device.
12. t
HZOE
13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
, t
HZCE
[13]
, t
HZBE
Read Cycle Time 55 70 ns
Address to Data Valid 55 70 ns
Data Hold from Address Change 10 10 ns
CE LOW to Data Valid 55 70 ns
OE LOW to Data Valid 25 35 ns
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[11]
[11, 12]
[11]
[11, 12]
5 5 ns
16 16 ns
10 10 ns
20 25 ns
CE LOW to Power-Up 0 0 ns
CE HIGH to Power-Down 55 70 ns
BLE / BHE LOW to Data Valid 55 70 ns
BLE / BHE LOW to Low Z
BLE / BHE HIGH to HIGH Z
[11]
[11, 12]
10 10 ns
20 25 ns
Write Cycle Time 55 70 ns
CE LOW to Write End 40 50 ns
Address Set-up to Write End 40 50 ns
Address Hold from Write End 0 0 ns
Address Set-up to Write Start 0 0 ns
WE Pulse Width 40 45 ns
BLE / BHE LOW to Write End 40 50 ns
Data Set-Up to Write End 25 30 ns
Data Hold from Write End 0 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
CC(typ.)
, and t
transitions are measured when the outputs enter a high impedence state.
HZWE
[11, 12]
[11]
is less than t
HZCE
LZCE
20 25 ns
10 10 ns
, t
is less than t
HZBE
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
CC(typ)
LZWE
/2, input
for any
Document #: 38-05343 Rev. *B Page 5 of 11
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Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
[14, 15]
t
RC
ADDRESS
t
t
OHA
AA
DATA OUT PREVIOUS DATA VALID DATA VALID
CY62147DV18
MoBL2™
t
ACE
[15, 16]
t
RC
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
t
DOE
BHE/BLE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDANCE
t
PU
CURRENT
Notes:
14. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
t
t
LZCE
LZBE
t
LZOE
t
DBE
50%
DATA VALID
t
t
HZBE
t
t
HZCE
HZOE
PD
50%
HIGH
IMPEDANCE
I
CC
I
SB
Document #: 38-05343 Rev. *B Page 6 of 11
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
ADDRESS
CE
[13, 17, 18]
t
SCE
t
CY62147DV18
MoBL2™
WC
t
WE
SA
BHE/BLE
OE
DATA I/O
NOTE
19
t
HZOE
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
WE
[13, 17, 18]
t
SA
t
AW
t
PWE
t
BW
t
SD
DATA
IN
t
WC
t
SCE
t
AW
t
PWE
t
HA
t
HD
t
HA
t
BHE/BLE
BW
OE
t
SD
DATA I/O
Notes:
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
NOTE
19
t
HZOE
DATA
IN
t
HD
Document #: 38-05343 Rev. *B Page 7 of 11
[+] Feedback
Switching Waveforms (continued)
[18]
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
BHE/BLE
t
t
BW
SCE
t
CY62147DV18
MoBL2™
WC
t
SA
WE
DATAI/O
NOTE 19
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
ADDRESS
CE
BHE/BLE
t
SA
WE
t
HZWE
DATA I/O
NOTE 19
t
AW
t
PWE
t
SD
t
HA
t
HD
DATAIN
t
LZWE
[18]
t
WC
t
SCE
t
AW
t
BW
t
PWE
t
SD
DATA
IN
t
HA
t
HD
t
LZWE
Document #: 38-05343 Rev. *B Page 8 of 11
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CY62147DV18
MoBL2™
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
X X X H H High Z Deselect/Power-Down Standby (ISB)
L H L L L Data Out (I/OO–I/O15) Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15) Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
in High Z
15
in High Z
15
Ordering Information
Speed
(ns) Ordering Code
55 CY62147DV18L-55BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial
CY62147DV18LL-55BVI
70 CY62147DV18L-70BVI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Industrial
CY62147DV18LL-70BVI
55 CY62147DV18L-55BVXI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free Industrial
CY62147DV18LL-55BVXI
70 CY62147DV18L-70BVXI BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Pb-free Industrial
CY62147DV18LL-70BVXI
Package
Name Package Type
Read (Lower byte only) Active (ICC)
Read (Higher byte only) Active (ICC)
Write (Lower byte only) Active (ICC)
Write (Higher byte only) Active (ICC)
Operating
Range
Document #: 38-05343 Rev. *B Page 9 of 11
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Package Diagram
CY62147DV18
MoBL2™
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05343 Rev. *B Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypres s Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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Document History Page
Document Title:CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM
Document Number: 38-05343
REV. ECN NO.
Date
** 127482 06/17/03 HRT New Data Sheet
*A 131009 11/26/03 CBD Changed From Advance to Preliminary
*B 229908 See ECN AJU Changed From Preliminary to Final
Issue
Orig. of
Change Description of Change
Added 70 ns speed bin
Changed Vcc MAX spec from 2.20V to 2.25V
Modified VIH spec on footnote #6 from V
Changed ICC TYP values from 8 mA to 6 mA
Changed ICC MAX values at Vcc (max) = 1.95V from 15 mA to 12 mA (L bin)
and 10 mA to 8mA (LL bin)
Changed ICC MAX values at Vcc (max) = 2.25V from 18 mA to 15 mA (L bin)
and 12mA to 10 mA (LL bin)
With modified V
to 18 uA (L bin) and 10 uA to 12 uA (LL bin)
spec, changed I
cc MAX
Modified input and output capacitance values
Removed footnote #9 from earlier rev
Removed MAX value for V
Modified t
Added Pb-free ordering information
from 20 ns to 16 ns
HZOE
DR
CC (MAX)
and I
SB1
CY62147DV18
MoBL2™
+ 0 .5V t o V
MAX values from 15 uA
SB2
CC (MAX)
+ 0.75V
Document #: 38-05343 Rev. *B Page 11 of 11
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