Cypress CY62146EV30 User Manual
CY62146EV30 MoBL
®
4-Mbit (256K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62146DV30
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
, and OE features
[1]
®
) in
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE
IO
) are placed in a high impedance state when:
15
HIGH). The input and output pins (IO0 through
• Deselected (CE HIGH)
• Outputs are disabled (OE
HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE
, BLE HIGH)
• Write operation is active (CE
LOW and WE LOW)
Write to the device by taking Chip Enable (CE) and Write
Enable (WE
then data from IO pins (IO
location specified on the address pins (A
High Enable (BHE
) inputs LOW. If Byte Low Enable (BLE) is LOW,
through IO7), is written into the
0
through A17). If Byte
0
) is LOW, then data from IO pins (IO
through IO15) is written into the location specified on the
address pins (A
Read from the device by taking Chip Enable (CE
Enable (OE
If Byte Low Enable (BLE
location specified by the address pins appear on IO
Byte High Enable (BHE
appears on IO
through A17).
0
) and Output
) LOW while forcing the Write Enable (WE) HIGH.
) is LOW, then data from the memory
to IO7. If
0
) is LOW, then data from memory
to IO15. See the “Truth Table” on page 9 for a
8
complete description of read and write modes.
8
Product Portfolio
Power Dissipation
Product VCC Range (V)
Min Typ
[2]
Max Typ
CY62146EV30LL 2.2 3.0 3.6 45 ns 2 2.5 15 20 1 7
Notes:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05567 Rev. *C Revised March 26, 2007
Speed
(ns)
Operating ICC (mA)
f = 1 MHz f = f
[2]
Max Typ
[2]
CC
max
Max Typ
= V
CC(typ)
Standby I
, TA = 25°C.
(µA)
SB2
[2]
Max
Logic Block Diagram
CY62146EV30 MoBL
®
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
SENSE AMPS
IO
–IO
0
IO8–IO
7
15
COLUMN DECODER
BHE
WE
11
13
15
A12A
14
A
A
17
16
A
A
A
CE
OE
BLE
Pin Configurations
BLE
IO
IO
V
SS
V
CC
IO
IO
NC
[3, 4]
48-ball VFBGA
OE
BHE
8
IO
10
9
IO
11
IO
12
IO
13
14
NC
15
A
8
Top Vi e w
41
326
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
5
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
IO
IO
IO
IO
WE
A
NC
2
IO
IO
1
V
3
V
4
IO
5
11
CC
IO
NC
SS
A
B
0
C
2
D
E
F
6
G
7
H
44-pin TSOP II
A
1
4
A
2
3
A
3
2
A
4
1
A
5
0
6
CE
IO
7
0
IO
8
1
IO
9
2
IO
10
3
V
11
CC
V
12
SS
IO
13
4
IO
14
5
IO
15
6
IO
16
7
17
WE
A
18
17
A
16
19
A
15
20
A
14
21
A
13
22
Top Vi e w
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
IO
IO
14
IO
IO
V
SS
V
CC
IO
11
IO
IO
IO
8
NC
A
8
A
9
A
10
A
11
A
12
15
13
12
10
9
Notes:
3. NC pins are not connected on the die.
4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
Document #: 38-05567 Rev. *C Page 2 of 12
CY62146EV30 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ..................................................... >200 mA
Operating Range
Supply Voltage to Ground
Potential .............................–0.3V to + 3.9V (V
DC Voltage Applied to Outputs
in High-Z State
[5, 6]
................–0.3V to 3.9V (V
CCmax
CCmax
+ 0.3V)
+ 0.3V)
Device Range
CY62146EV30 Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
OH
OL
IH
IL
Output HIGH Voltage IOH = –0.1 mA 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 V
CC
Output LOW Voltage IOL = 0.1 mA 0.4 V
= 2.1 mA, V
I
OL
Input HIGH Voltage V
Input LOW Voltage V
= 2.2V to 2.7V 1.8 V
CC
V
= 2.7V to 3.6V 2.2 V
CC
= 2.2V to 2.7V –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
Input Leakage Current GND < VI < V
> 2.70V 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
VCC Operating Supply Current f = f
Automatic CE Power down
Current — CMOS Inputs
= 1/t
max
f = 1 MHz 2 2.5
> VCC−0.2V,
CE
V
> VCC–0.2V or V
IN
f = f
f = 0 (OE
(Address and Data Only),
max
, BHE, BLE and WE), V
RC
VCC = V
I
= 0 mA
OUT
CMOS levels
< 0.2V
IN
CC(max),
CC
[5, 6]
........... –0.3V to 3.9V (V
Temperature V
–1 +1 µA
= 3.60V
CC max
Ambient
45 ns
[2]
Max
+ 0.3 V
CC
+ 0.3 V
CC
15 20 mA
17µA
+ 0.3V)
[7]
CC
UnitMin Typ
[8]
I
SB2
Notes:
5. V
IL(min)
6. V
IH(max)
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
8. Only chip enable (CE
Automatic CE Power down
Current — CMOS Inputs
= –2.0V for pulse durations less than 20 ns.
= V
+ 0.75V for pulse durations less than 20 ns.
CC
) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
CE
> VCC – 0.2V,
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, V
= 3.60V
CC
(min) and 200 µs wait time after V
cc
SB2
17µA
stabilization.
cc
/ I
spec. Other inputs can be left floating.
CCDR
Document #: 38-05567 Rev. *C Page 3 of 12
CY62146EV30 MoBL
®
Capacitance (For All Packages)
[9]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Thermal Resistance
Parameter Description Test Conditions
Θ
Θ
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
[9]
CC(typ)
VFBGA
Package
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
75 77 °C/W
10 13 °C/W
10 pF
TSOP II
Package Unit
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
JIG AND
SCOPE
30 pF
R1
VCC
10%
R2
Rise Time = 1 V/ns
GND
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT V
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[10]
t
R
[9]
VCC for Data Retention 1.5 V
[8]
Data Retention Current V
= 1.5V, CE > VCC – 0.2V,
CC
V
> VCC – 0.2V or VIN < 0.2V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
RC
Data Retention Waveform
DATA RETENTION MODE
V
V
CC
CE
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full device operation requires linear V
ramp from V
CC
CC(min)
t
CDR
DR
to V
> 100 µs or stable at V
CC(min)
VDR> 1.5V
CC(min)
> 100 µs.
V
CC(min)
t
R
[2]
Max Unit
0.8 7 µA
ns
Document #: 38-05567 Rev. *C Page 4 of 12
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