Cypress CY62146E User Manual
CY62146E MoBL
®
4-Mbit (256K x 16) Static RAM
Features
256K x 16
RAM Array
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A12A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO8–IO
15
CE
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
A
17
Logic Block Diagram
■ Very high speed: 45 ns
■ Wide voltage range: 4.5V–5.5V
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Available in Pb-free 44-pin TSOP II package
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life™ (MoBL
cations such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
®
) in portable appli-
mode reduces power consumption by more than 99% when
deselected (CE
) are placed in a high impedance state when:
IO
15
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE
, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE
(WE
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
specified on the address pins (A
Enable (BHE
HIGH). The input and output pins (IO0 through
) and Write Enable
through IO7) is written into the location
0
) is LOW, then data from IO pins (IO8 through IO15)
through A17). If Byte High
0
is written into the location specified on the address pins (A
through A17).
To read from the device, take Chip Enable (CE
Enable (OE
Byte Low Enable (BLE
) LOW while forcing the Write Enable (WE) HIGH. If
) is LOW, then data from the memory
location specified by the address pins appea rs on IO
Byte High Enable (BHE
appears on IO
of read and write modes.
to IO15. See Table 1 for a complete description
8
) is LOW, then data from memory
) and Output
to IO7. If
0
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-07970 Rev. *D Revised February 01, 2008
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CY62146E MoBL
®
Pin Configuration
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
15
A
16
A
8
A
9
A
10
A
11
A
13
A
14
A
12
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
17
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
Figure 1. 44-Pin TSOP II (Top View)
[1]
Product Portfolio
Product Range
VCC Range (V)
Min Typ
[2]
Max Typ
CY62146ELL Ind’l/Auto-A 4.5 5.0 5.5 45 2 2.5 15 20 1 7
Document Number: 001-07970 Rev. *D Page 2 of 11
Speed
(ns)
Power Dissipation
Operating ICC, (mA)
f = 1 MHz f = f
[2]
Max Typ
[2]
max
Max Typ
Standby, I
(μA)
[2]
SB2
Max
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CY62146E MoBL
®
Maximum Ratings
Notes
3. V
IL
(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.
4. V
IH
(max) = VCC + 0.75V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after VCC stabilization.
6. Only chip enable (CE
) and byte enables (BHE and BLE) is tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs are left floating.
Exceeding maximum ratings may impair the useful life of th e
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
DC Input Voltage
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch up Current............................................... .......>200 mA
Operating Range
Supply Voltage to Ground Potential..................–0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State
[3, 4]
..........................................–0.5V to 6.0V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB2
OH
OL
IH
IL
[6]
Output HIGH Voltage IOH = –1.0 mA 2.4 V
Output LOW Voltage IOL = 2.1 mA 0.4 V
Input HIGH Voltage 4.5 < VCC < 5.5 2.2 V
Input LOW Voltage 4.5 < VCC < 5.5 –0.5 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 μA
VCC Operating Supply
Current
Automatic CE Power
down Current — CMOS
f = f
= 1/t
max
RC
f = 1 MHz 2 2.5
CE
> VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, V
CC
V
=
CC(max)
VCC = V
I
OUT
Inputs
[3, 4]
.......................................–0.5V to 6.0V
Device Range
Ambient
Temperature
[5]
V
CC
CY62146ELL Ind’l/Auto-A –40°C to +85°C 4.5V–5.5V
45 ns (Ind’l/Auto-A)
[2]
Max
+ 0.5 V
CC
UnitMin Typ
–1 +1 μA
CCmax
15 20 mA
= 0 mA, CMOS levels
17μA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions TSOP II Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch, two layer
printed circuit board
77 °C/W
13 °C/W
Document Number: 001-07970 Rev. *D Page 3 of 11
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CY62146E MoBL
®
Figure 2. AC Test Loads and Waveforms
VCC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
TH
Notes
7. T ested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
V
CC(min)
V
CC(min)
t
CDR
VDR> 2.0V
DATA RETENTION MODE
t
R
V
CC
CE
Parameters 5.0V Unit
R1 1800 Ω
R2 990 Ω
R
TH
V
TH
639 Ω
1.77 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[8]
t
R
[7]
VCC for Data Retention 2 V
[6]
Data Retention Current
= 2V, CE > VCC – 0.2V,
V
CC
VIN > VCC – 0.2V or VIN < 0.2V
Chip Deselect to Data
0ns
Retention Time
Operation Recovery Time t
RC
[2]
Max Unit
17μA
ns
Figure 3. Data Retention Waveform
Document Number: 001-07970 Rev. *D Page 4 of 11
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