• Ultra-low active power
—Typical active current: 1.5 mA @ f = 1 MHz
—Ty pical active curre nt: 7 mA @ f = f
(70 ns speed)
max
• Low standby power
• Easy memory expansion with CE
and OE features
• Automatic power-down when deselec ted
• CMOS for optimum speed/power
Functional Description
The CY62146CV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by 99% when deselected (CE
HIGH). The input/output pins (I/O0 – I/ O15) are placed in a
high-impeda nce state when : deselected (CE
are disabled (OE
Enable are disabled (BHE
operation (CE
HIGH), both Byte High Enable an d Byte Low
, BLE HIGH), or during a Write
LOW and WE LOW).
HIGH), outputs
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
) is LOW, then data from I/O pins (I/O0 – I/O7), is written
(BLE
into the location specified on the address pins (A
Byte High Enable (BHE
– I/O15) is written into the location specified on the
(I/O
8
address pins (A
– A17).
0
) is LOW, then data from I/O pins
– A17). If
0
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the Truth Table on page 9 for a complete description of Read
– I/O7. If Byte High Enable (BHE) is
0
to I/O15. See
8
and Write mode s.
The CY62146CV30 is available in 48-ball FBGA packaging.
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K × 16
RAM Array
2048 × 2048
COLUMN DECODER
11
12
A
A
15
13
A
16
14
A
A
A
– I/O
I/O
0
7
SENSE AMPS
17
A
I/O8 – I/O
BHE
WE
CE
OE
BLE
15
Cypress Semiconductor Corporation•3901 North First Street•San Jose•CA 95134•408-943-2600
Document #: 38-05203 Rev. ** Revised December 17, 2001
CY62146CV30 MoBL™
Pin Configuration
[1,2]
Product Portfolio
1
BLE
I/O
I/O
V
SS
V
CC
I/O
I/O
NC
2
OE
BHE
8
I/O
10
9
I/O
11
I/O
12
I/O
13
14
NC
15
A
8
FBGA (Top View)
4
3
A
A
0
1
A
A
4
3
A
A
5
6
A
A
DNU
7
17
A
16
A
A
15
14
A
A
13
12
A
A
10
9
A
CE
I/O
I/O
I/O
I/O
WE
A
5
6
NC
2
I/O
I/O
1
V
3
V
4
I/O
5
I/O
NC
11
A
B
0
C
2
cc
D
ss
E
F
6
G
7
H
Power Dissipation (Industrial)
V
Range
Product
V
CC(min.)VCC(typ.)
CY62146CV302.7V3.0V3.3V
Maximum Ratings
(Above which the useful life may be im pa ired . Fo r us er gui delines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...–0.5V to V
DC Voltage Applied to Outputs
in High-Z State
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or V
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
4. V
IL(min.)
[4]
....................................–0.5V to VCC + 0.5V
= –2.0V for pulse durations less than 20 ns.
CC
[3]
V
CC(max.)
ccmax
to ensure proper appl ication.
SS
Speed
Typ.
55 ns1.5 mA 3 mA12 mA 25 mA
70 ns1.5 mA 3 mA7 mA15 mA
DC Input Voltage
Output Current into Outputs (LOW).............................20 mA