CY62138FV30 MoBL
®
2-Mbit (256K x 8) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62138CV25/30/33
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
, CE2, and OE features
1
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Logic Block Diagram
Functional Description
[1]
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Place the device into standby
mode reducing power consumption when deselected (CE
HIGH or CE2 LOW).
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
specified on the address pins (A
through IO7) is then written into the location
0
through A17).
0
LOW and CE
1
To read from the device, take Chip Enable (CE1 LOW and CE
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
in a high impedance state when the device is deselected (CE
through IO7) are placed
0
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
LOW).
LOW and CE2 HIGH and WE
1
1
2
2
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
9
10
11
ROW DECODER
A
A
CE
1
CE
2
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
A
WE
OE
DATA IN DRIVERS
256K x 8
ARRAY
COLUMN DECODER
14
16
13
12
A
A15A
A
A
SENSE AMPS
POWER
DOWN
17
A
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-08029 Rev. *E Revised March 26, 2007
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CY62138FV30 MoBL
®
Pin Configuration
36-Ball VFBGA
A
A
1
0
IO
A
4
2
IO
5
V
SS
V
CC
IO
6
IO
OE
7
A
A
10
9
[2]
Top View
CE
2
WE
NC
NC
CE
1
A
11
32-Pin SOIC/TSOP II
Top Vi e w
A
A
3
A
4
A
5
A
17
A
16
A
12
A
6
A
IO
7
IO
V
V
IO
IO
A
15
A
A
13
8
CC
SS
14
A
B
0
C
1
D
E
F
2
G
3
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
12
0
IO
13
0
IO
1
14
IO
15
2
V
16
SS
V
CC
32
A
31
15
CE
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
A
A
A
A
OE
A
CE
IO
IO
IO
IO
IO
2
13
8
9
11
10
1
7
6
5
4
3
H
A
1
11
2
A
9
3
A
8
4
A
13
5
WE
6
CE
2
7
A
15
8
V
CC
9
A
17
A
10
16
A
11
14
A
12
12
A
13
7
A
14
6
15
A
5
16
A
4
TSOP I
Top V i e w
(not to scale)
32
OE
31
A
10
30
CE
1
29
IO
7
28
IO
6
27
IO
5
26
IO
4
25
IO
3
24
GND
IO
23
2
22
IO
1
IO
21
0
A
20
0
A
19
1
18
A
2
A
17
3
A
11
25
A
9
26
A
26
27
8
28
A
13
29
WE
30
CE
2
31
A
15
32
V
CC
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
7
A
5
8
A
4
STSOP
Top V iew
(not to scale)
24
OE
23
A
10
22
CE
1
21
IO
7
20
IO
6
19
IO
5
18
IO
4
17
IO
3
16
GND
IO
15
2
14
IO
1
IO
13
0
A
12
0
A
11
1
10
A
2
A
9
3
Product Portfolio
Power Dissipation
V
Product
Range (V)
CC
Min Typ
[3]
Max Typ
Speed
(ns)
Operating I
f = 1 MHz f = f
[3]
Max Typ
CY62138FV30LL 2.2 3.0 3.6 45 1.6 2.5 13 18 1 5
CC
(mA)
[3]
max
Max Typ
Standby I
[3]
SB2
(µA)
Max
Note
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, TA = 25°C.
Document #: 001-08029 Rev. *E Page 2 of 13
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CY62138FV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
DC Input Voltage
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Power Applied...............................................55°C to +125°C
Supply Voltage to Ground
Potential........................................................... –0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
.......................................... –0.3V to 3.9V
CY62138FV30LL Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[7]
Output HIGH Voltage IOH = –0.1 mA 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 V
CC
Output LOW Voltage IOL = 0.1 mA 0.4 V
= 2.1 mA, V
I
OL
Input HIGH Voltage V
Input LOW Voltage V
= 2.2V to 2.7V 1.8 V
CC
= 2.7V to 3.6V 2.2 V
V
CC
= 2.2V to 2.7V For BGA package –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
= 2.2V to 3.6V For other packages –0.3 0.6 V
V
CC
Input Leakage Current GND < VI < V
> 2.70V 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC,
output disabled
VCC Operating Supply Current f = f
Automatic CE Power Down
Current CMOS Inputs
Automatic CE Power Down
Current CMOS Inputs
= 1/t
max
RC
f = 1 MHz 1.6 2.5
CE1 > V
VIN > V
f = f
f = 0 (OE
– 0.2V or CE2 < 0.2V,
CC
– 0.2V, V
CC
(address and data only),
max
, and WE), V
VCC = V
I
= 0 mA
OUT
CMOS levels
< 0.2V),
IN
= 3.60V
CC
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, V
= 3.60V
CC
[4, 5]
.......................................–0.3V to 3.9V
Product Range
Min Typ
–1 +1 µA
–1 +1 µA
CCmax
Ambient
Temperature
V
45 ns
[3]
Max
+ 0.3V V
CC
+ 0.3V V
CC
13 18 mA
15µA
15µA
CC
[6]
Unit
Capacitance (For all packages)
[8]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Notes
4. V
5. V
6. Full device AC operation assumes a 100 µs ramp time from 0 to V
7. Only chip enables (CE
8. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min)
= VCC+0.75V for pulse durations less than 20 ns.
IH(max)
Input Capacitance TA = 25°C, f = 1 MHz,
= V
V
CC
Output Capacitance 10 pF
and CE2) must be at CMOS level to meet the I
1
CC(typ.)
(min) and 200 µs wait time after V
CC
/ I
SB2
spec. Other inputs can be left floating.
CCDR
stabilization.
CC
10 pF
Document #: 001-08029 Rev. *E Page 3 of 13
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CY62138FV30 MoBL
®
Thermal Resistance
[8]
Parameter Description Test Conditions SOIC VFBGA TSOP II STSOP TSOP I Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still air, soldered on a 3 x 4.5
inch, two layer printed circuit
board
44.53 38.49 44.16 59.72 50.19 °C/W
24.05 17.66 11.97 15.38 14.59 °C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
30 pF
R2
V
CC
GND
Rise Time = 1 V/ns
INCLUDING
R1
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
R
OUTPUT V
Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
ALL INPUT PULSES
10%
TH
90%
90%
10%
Fall Time = 1 V/ns
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[8]
t
CDR
[9]
t
R
Data Retention Waveform
Notes:
9. Full device AC operation requires linear V
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
10. CE
VCC for Data Retention 1.5 V
[7]
Data Retention Current VCC = 1.5V,
CE
> VCC − 0.2V or CE2 < 0.2V,
1
V
> VCC − 0.2V or VIN < 0.2V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
[10]
DATA RETENTION MODE
V
ramp from V
CC
CC(min)
t
CDR
DR
to V
> 100 µs or stable at V
CC(min)
V
CC
CE
VDR> 1.5V
CC(min)
> 100 µs.
RC
V
CC(min)
t
R
[3]
Max Unit
14µA
ns
Document #: 001-08029 Rev. *E Page 4 of 13
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CY62138FV30 MoBL
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[14]
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid 22 ns
OE LOW to Low-Z
OE HIGH to High-Z
[12]
[12,13]
CE1 LOW and CE2 HIGH to Low Z
CE1 HIGH or CE2 LOW to High-Z
[12, 13]
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH or CE2 LOW to Power Down
Write Cycle Time 45 ns
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End 35 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 35 ns
Data Setup to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High-Z
WE HIGH to Low-Z
[12, 13]
[12]
[12]
[11]
45 ns
Unit
Min Max
45 ns
5ns
18 ns
10 ns
18 ns
0ns
45 ns
35 ns
18 ns
10 ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
pulse levels of 0 to V
12. At any given temperature and voltage condition, t
, t
13. t
HZOE
14. The internal write time of the memory is defined by the overlap of WE
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.
HZCE
, and t
, and output loading of the specified IOL/IOH as shown in the ““AC Test Loads and Waveforms” on page 4” .
CC(typ)
transitions are measured when the output enters a high impedance state.
HZWE
is less than t
HZCE
, t
LZCE
, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
is less than t
HZOE
LZOE
, and t
is less than t
HZWE
for any given device.
LZWE
CC(typ)
/2, input
Document #: 001-08029 Rev. *E Page 5 of 13
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Switching Waveforms
Read Cycle 1 (Address transition controlled)
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID DATA VALID
[15, 16]
CY62138FV30 MoBL
tRC
RC
t
AA
®
Read Cycle No. 2 (OE controlled)
ADDRESS
CE
OE
HIGH IMPEDANCE
DATA OUT
V
CC
SUPPLY
t
LZCE
t
PU
CURRENT
Write Cycle No. 1 (WE controlled)
ADDRESS
CE
[10, 16, 17]
t
ACE
t
DOE
t
LZOE
50%
[10, 14, 18, 19]
t
t
SCE
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
I
CC
50%
I
SB
t
WC
t
AW
t
SA
t
PWE
t
HA
WE
OE
20
DATA IO
Notes:
15. The device is continuously selected. OE
is HIGH for read cycle.
16. WE
17. Address valid before or similar to CE
18. Data IO is high impedance if OE
goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
19. If CE
1
20. During this period, the IOs are in output state. Do not apply input signals.
NOTE
t
HZOE
, CE1 = VIL, CE2 = VIH.
transition LOW and CE2 transition HIGH.
1
= VIH.
t
SD
DATA VALID
t
HD
Document #: 001-08029 Rev. *E Page 6 of 13
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Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 controlled)
ADDRESS
CE
t
SA
WE
[10, 14, 18, 19]
CY62138FV30 MoBL
t
WC
t
SCE
t
AW
t
PWE
t
HA
®
DATA IO
Write Cycle No. 3 (WE controlled, OE LOW)
ADDRESS
CE
t
SA
WE
20
DATA IO
NOTE
t
HZWE
[10, 19]
t
AW
t
SCE
t
SD
t
HD
DATA VALID
t
WC
t
HA
t
PWE
t
SD
t
HD
DATA VALID
t
LZWE
Truth Table
CE
H X X X High-Z Deselect/Power Down Standby (I
X L X X High-Z Deselect/Power Down Standby (I
L H H L Data Out Read Active (ICC)
L H H H High-Z Output Disabled Active (I
L H L X Data in Write Active (I
Document #: 001-08029 Rev. *E Page 7 of 13
CE
1
WE OE Inputs/Outputs Mode Power
2
CC
CC
SB
SB
)
)
)
)
[+] Feedback
CY62138FV30 MoBL
Ordering Information
Speed
(ns)
Ordering Code
45 CY62138FV30LL-45BVXI 51-85149 36-ball VFBGA (Pb-free) Industrial
CY62138FV30LL-45ZSXI 51-85095 32-pin TSOP II (Pb-free)
CY62138FV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free)
CY62138FV30LL-45ZXI 51-85056 32-pin TSOP I (Pb-free)
CY62138FV30LL-45SXI 51-85081 32-pin SOIC (Pb-free)
Package Diagrams
Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149
Package
Diagram
Package Type
Operating
®
Range
0.25 C
8.00±0.10
A
0.55 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
B
6.00±0.10
0.21±0.05
0.10 C
8.00±0.10
A
0.75
5.25
2.625
B
0.15(4X)
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(36X)
65
1.875
0.75
3.75
6.00±0.10
A1 CORNER
234
1
A
B
C
D
E
F
G
H
SEATING PLANE
C
51-85149-*C
0.26 MAX.
1.00 MAX
Document #: 001-08029 Rev. *E Page 8 of 13
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Package Diagrams (continued)
Figure 2. 32-pin TSOP II, 51-85095
CY62138FV30 MoBL
®
51-85095-**
Document #: 001-08029 Rev. *E Page 9 of 13
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Package Diagrams (continued)
Figure 3. 32-pin (450 Mil) Molded SOIC, 51-85081
17 32
116
0.440[11.176]
0.450[11.430]
0.546[13.868]
0.566[14.376]
CY62138FV30 MoBL
®
0.101[2.565]
0.111[2.819]
0.050[1.270]
BSC.
0.793[20.142]
0.817[20.751]
0.014[0.355]
0.020[0.508]
0.004[0.102]
SEATING PLANE
MIN.
0.118[2.997]
MAX.
0.004[0.102]
0.006[0.152]
0.012[0.304]
0.023[0.584]
0.039[0.990]
0.047[1.193]
0.063[1.600]
51-85081-*B
Document #: 001-08029 Rev. *E Page 10 of 13
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Package Diagrams (continued)
Figure 4. 32-pin TSOP I (8 x 20 mm), 51-85056
CY62138FV30 MoBL
®
51-85056-*D
Document #: 001-08029 Rev. *E Page 11 of 13
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Package Diagrams (continued)
Figure 5. 32-pin STSOP (8 x 13.4 mm), 51-85094
CY62138FV30 MoBL
®
51-85094-*D
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 001-08029 Rev. *E Page 12 of 13
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62138FV30 MoBL
Document History Page
Document Title: CY62138FV30 MoBL®, 2-Mbit (256K x 8) Static RAM
Document Number: 001-08029
REV. ECN NO.
Issue
Date
** 463660 See ECN NXR New data sheet
*A 467351 See ECN NXR Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages
*B 566724 See ECN NXR Converted from Preliminary to Final
*C 797956 See ECN VKN Added 32-pin SOIC package
*D 809101 See ECN VKN Corrected typo in the Ordering Information table
*E 940341 See ECN VKN Added footnote #7 related to I
Orig. of
Change
Description of Change
Changed ball A3 from NC to CE
in 36-ball FBGA pin out
2
Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed
pin 24 from CE
Changed the I
Changed the I
Changed the I
Changed the I
µA to 4 µA
to OE and pin 22 from CE to CE1)
1
value from 2.25 mA to 2.5 mA for test condition f=1 MHz
CC(max)
value from 0.5 µA to 1 µA
SB2(typ)
SB2(max)
CCDR(typ)
value from 2.5 µA to 5 µA
value from 0.5 µA to 1 µA and I
CCDR(max)
value from 2.5
Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical
characteristics table
and I
SB2
CCDR
®
Document #: 001-08029 Rev. *E Page 13 of 13
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