Cypress CY62138F User Manual
CY62138F MoBL
®
2-Mbit (256K x 8) Static RAM
Features
• High speed: 45 ns
• Wide voltage range: 4.5 V – 5.5 V
• Pin compatible with CY62138V
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
, CE2, and OE features
1
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II
packages
Logic Block Diagram
Functional Description
[1]
The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
LOW).
or CE
2
HIGH
1
To write to the device, take Chip Enable (CE1 LOW and CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
specified on the address pins (A
To read from the device, take Chip Enable (CE
HIGH) and output enable (OE) LOW while forcing Write
Enable (WE
through IO7) is then written into the location
0
through A17).
0
LOW and CE
1
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
in a high impedance state when the device is deselected (CE
through IO7) are placed
0
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
LOW).
LOW and CE2 HIGH and WE
1
2
2
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
9
10
11
ROW DECODER
A
A
CE
1
CE
2
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
A
WE
OE
DATA IN DRIVERS
256K x 8
ARRAY
COLUMN DECODER
14
16
13
12
A
A15A
A
A
SENSE AMPS
POWER
DOWN
17
A
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-13194 Rev. *A Revised March 26, 2007
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CY62138F MoBL
®
Pin Configuration
Product Portfolio
Product
[2]
VCC Range (V)
Min Typ
32-Pin SOIC/TSOP II Pinout
Top View
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
12
0
IO
13
0
IO
1
14
IO
15
2
V
16
SS
V
CC
32
A
31
15
CE
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
A
A
A
A
OE
A
CE
IO
IO
IO
IO
IO
2
13
8
9
11
10
1
7
6
5
4
3
Power Dissipation
Speed
(ns)
[3]
Max Typ
Operating ICC (mA)
f = 1MHz f = f
[3]
Max Typ
[3]
max
Max Typ
Standby I
[3]
SB2
(µA)
Max
CY62138FLL 4.5V 5.0V 5.5V 45 1.6 2.5 13 18 1 5
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
Document #: 001-13194 Rev. *A Page 2 of 10
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CY62138F MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential ................................–0.5V to 6.0V (V
DC Voltage Applied to Outputs
in High-Z state
[4, 5]
................–0.5V to 6.0V (V
CCmax
CCmax
+ 0.5V)
+ 0.5V)
DC Input Voltage
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB2
OH
OL
IH
IL
[7]
Output HIGH Voltage IOH = –1.0 mA 2.4 V
Output LOW Voltage IOL = 2.1 mA 0.4 V
Input HIGH Voltage V
Input LOW Voltage V
Input Leakage Current GND < VI < V
= 4.5V to 5.5V 2.2 V
CC
= 4.5V to 5.5V –0.5 0.8 V
CC
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA
VCC Operating Supply
Current
Automatic CE Power Down
Current CMOS inputs
f = f
= 1/t
max
RC
f = 1 MHz 1.6 2.5
CE1 > VCC – 0.2V or CE2 < 0.2V
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, VCC = V
CC(max)
[4, 5]
............ –0.5V to 6.0V (V
Device Range
Ambient
Temperature
CCmax
+ 0.5V)
V
CC
[6]
CY62138FLL Industrial –40°C to +85°C 4.5V to 5.5V
45 ns
Min Typ
[3]
Max
+ 0.5 V
CC
Unit
–1 +1 µA
VCC = V
I
OUT
CMOS levels
CC(max)
= 0 mA
13 18 mA
15µA
Capacitance (For all packages)
[8]
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input capacitance TA = 25°C, f = 1 MHz,
Output capacitance 10 pF
Thermal Resistance
= V
V
CC
CC(typ)
[8]
10 pF
Parameter Description Test Conditions SOIC TSOP II Unit
Θ
JA
Θ
JC
Notes
4. V
5. V
6. Full device AC operation assumes a 100 µs ramp time from 0 to V
7. Only chip enables (CE
8. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min)
= VCC+0.75V for pulse durations less than 20ns.
IH(max)
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch
two-layer printed circuit board
Thermal Resistance
(Junction to Case)
and CE2) must be at CMOS level to meet the I
1
(min) and 200 µs wait time after V
CC
/ I
SB2
spec. Other inputs can be left floating.
CCDR
44.53 44.16 °C/W
24.05 11.97 °C/W
stabilization.
CC
Document #: 001-13194 Rev. *A Page 3 of 10
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