CY62138EV30
MoBL
®
2-Mbit (256K x 8) MoBL® Static RAM
Features
• Very high speed: 45 ns
— Wide voltage range: 2.20V – 3.60V
• Pin-compatible with CY62138CV30
• Ultra-low standby power
— Typical standby current: 1 µA
— Maximum standby current: 7 µA
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE
and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in Pb-free 36-ball BGA package
Logic Block Diagram
Functional Description
[1]
The CY62138EV30 is a high-performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE
HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
through I/O7) is then written into the location
0
through A18).
0
Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE
) and Output Enable (OE) LOW while forcing Write
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW and WE LOW).
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
Data in Drivers
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
A
9
A
10
A
11
CE
WE
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
256K x 8
ARRAY
COLUMN
DECODER
13
12
A
A
SENSE AMPS
POWER
DOWN
14
16
17
15
A
A
A
A
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05577 Rev. *A Revised February 14, 2006
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CY62138EV30
MoBL
®
Pin Configuration
[2]
FBGA
Top View
A
A
I/O
I/O
V
V
I/O
I/O
A
0
SS
CC
9
A
1
WE
A
4
2
OE
A
NC
NC
10
5
6
7
CE
A
3
A
4
A
5
A
17
A
16
A
12
11
A
NC
A
6
A
I/O
7
I/O
V
V
I/O
I/O
A
15
A
A
13
A
8
B
0
C
1
D
cc
E
ss
F
2
G
3
H
14
Product Portfolio
Power Dissipation
Product
V
Range (V)
CC
Min. Typ.
[3]
Max. Typ.
Speed
(ns)
Operating I
[3]
Max. Typ.
CY62138EV30LL 2.2 3.0 3.6 45 2 2.5 15 20 1 7
Notes:
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
(mA)
[3]
max
Max. Typ.
= V
CC
CC(typ.)
Standby I
[3]
, TA = 25°C.
SB2
(µA)f = 1 MHz f = f
Max.
Document #: 38-05577 Rev. *A Page 2 of 9
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CY62138EV30
MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature..................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Supply Voltage to Ground
Potential........................................ –0.3V to V
DC Voltage Applied to Outputs
in High-Z State
[4,5]
.........................–0.3V to V
CC(MAX)
CC(MAX)
+ 0.3V
+ 0.3V
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Capacitance for all p ackages
C
IN
C
OUT
Notes:
4. V
IL(min.)
5. V
IH(max)
6. Full device AC operation assumes a 100 µs ramp time from 0 to V
Output HIGH Voltage IOH = –0.1 mAV
I
= –1.0 mAV
OH
Output LOW Voltage IOL = 0.1 mA V
IOL = 2.1 mA V
Input HIGH Voltage V
= 2.2V to 2.7V 1.8 V
CC
= 2.20V 2.0 V
CC
= 2.70V 2.4 V
CC
= 2.20V 0.4 V
CC
= 2.70V 0.4 V
CC
VCC= 2.7V to 3.6V 2.2 V
Input LOW Voltage V
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-down
Current — CMOS
Inputs
Automatic CE
Power-down
Current — CMOS
Inputs
[7]
= 2.2V to 2.7V –0.3 0.6 V
CC
V
= 2.7V to 3.6V –0.3 0.8 V
CC
GND < VI < V
CC
GND < VO < VCC,
Output Disabled
f = f
1/t
f = 1 MHz 2 2.5 mA
CE > V
V
Data Only), f = 0 (OE
V
=
MAX
RC
CC
< 0.2V), f = f
IN
= 3.60V
CC
VCC = V
I
OUT
CMOS levels
– 0.2V, V
MAX
= 0 mA
> V
IN
(Address and
, and WE),
CE > VCC – 0.2V,
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, V
= 3.60V
CC
Parameter Description Test Conditions Max. Unit
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
= –2.0V for pulse durations less than 20 ns.
= VCC+0.75V for pulse durations less than 20 ns.
V
(min.) and 200 µs wait time after V
CC
DC Input Voltage
[4,5]
......................–0.3V to V
CC(MAX)
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Ambient
Product Range
Temperature V
CY62138EV30LL Industrial –40°C to +85°C 2.2V to
CY62138EV30-45
[3]
Max.
+ 0.3V V
CC
+ 0.3V V
CC
–1 +1 µA
–1 +1 µA
CCmax
CC
– 0.2V,
15 20 mA
17µA
17µA
10 pF
= V
CC
CC(typ.)
stabilization.
CC
+ 0.3V
[6]
CC
3.6V
UnitMin. Typ.
Document #: 38-05577 Rev. *A Page 3 of 9
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CY62138EV30
Thermal Resistance
Parameter Description Test Conditions BGA Unit
MoBL
®
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air , soldered on a 3 x 4.5 inch, four-layer
printed circuit board
72 °C/W
8.86 °C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
INCLUDING
JIG AND
R1
ALL INPUT PULSES
10%
R
TH
90%
90%
10%
Fall time: 1 V/ns
TH
30 pF
SCOPE
VCC
R2
Equivalent to: THÉVENIN EQUIVALENT
GND
Rise Time: 1 V/ns
OUTPUT V
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
V
DR
I
CCDR
[7]
t
CDR
[8]
t
R
Data Retention Waveform
VCC for Data Retention 1 V
Data Retention Current VCC = 1V, CE > VCC − 0.2V,
V
> VCC − 0.2V or VIN < 0.2V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
RC
[3]
Max. Unit
0.8 3 µA
ns
DATA RETENTION MODE
V
CC
CE
Notes:
7. Tested initially and after any design or proc ess changes that may affect these parameters.
8. Full Device AC operation requires linear V
VCC (min.)
ramp from V
CC
t
CDR
DR
to V
> 100 µs or stable at V
CC(min.)
VDR> 1.5 V
CC(min.)
> 100 µs.
1.5V
t
R
Document #: 38-05577 Rev. *A Page 4 of 9
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CY62138EV30
MoBL
®
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[12]
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE LOW to Data Valid 45 ns
OE LOW to Data Valid 22 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[10]
[10,11]
[10]
[10, 11]
CE LOW to Power-up 0 ns
CE HIGH to Power-up 45 ns
Write Cycle Time 45 ns
CE LOW to Write End 35 ns
Address Set-up to Write End 35 ns
Address Hold from Write End 0 ns
Address Set-up to Write Start 0 ns
WE Pulse Width 35 ns
Data Set-up to Write End 25 ns
Data Hold from Write End 0 ns
WE LOW to High Z
WE HIGH to Low Z
[10, 11]
[10]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
[9]
45 ns
UnitMin. Max.
5ns
18 ns
10 ns
18 ns
18 ns
10 ns
t
RC
ADDRESS
t
t
OHA
DATA OUT PREVIOUS DATA VALID
Notes:
9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
input pulse levels of 0 to V
10.At any given temperature and voltage condition, t
, t
11. t
HZOE
12.The internal write time of the memory is defined by the overlap of WE
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13.Device is continuously selected. OE
14.WE
, and t
HZCE
is HIGH for read cycle.
HZWE
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
CC(typ)
transitions are measured when the output enter a high-impedance state .
, CE = VIL.
is less than t
HZCE
AA
DATA VALID
, t
LZCE
is less than t
HZOE
, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
LZOE
, and t
HZWE
is less than t
for any given device.
LZWE
CC(typ)
/2,
Document #: 38-05577 Rev. *A Page 5 of 9
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Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDANCE
CURRENT
Write Cycle No. 1 (WE Controlled)
[14, 15]
t
ACE
t
LZOE
t
LZCE
t
PU
[16, 18]
t
DOE
50%
CY62138EV30
HIGH
®
I
CC
I
SB
MoBL
t
RC
t
HZOE
t
HZCE
DATA VALID
t
PD
IMPEDANCE
50%
t
WC
ADDRESS
t
CE
WE
t
SA
SCE
t
AW
OE
DATA I/O
Notes:
15.Address valid prior to or coincident with CE
16.Data I/O is high impedance if OE
17.During this period, the I/Os are in output state and input signals should not be applied.
goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.
18.If CE
NOTE
17
= VIH.
t
HZOE
transition LOW.
t
PWE
t
SD
DATA
IN
VALID
t
HA
t
HD
Document #: 38-05577 Rev. *A Page 6 of 9
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Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
WE
OE
DATA I/O
Write Cycle No. 3 (WE Controlled, OE LOW)
[16, 18]
t
SA
[18]
CY62138EV30
MoBL
t
WC
t
SCE
t
HA
t
AW
t
PWE
t
SD
DATAIN VALID
t
HD
®
t
WC
ADDRESS
t
SCE
t
AW
t
PWE
t
SD
DATAINVALID
t
HA
t
LZWE
t
HD
CE
WE
DATA I/O
t
SA
NOTE 17
t
HZWE
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power-down Standby (ISB)
L H L Data Out (I/O
L H H High Z Output Disabled Active (I
L L X Data in (I/O0–I/O7) Write Active (ICC)
–I/O7) Read Active (ICC)
0
CC
)
Document #: 38-05577 Rev. *A Page 7 of 9
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CY62138EV30
MoBL
Ordering Information
Speed
(ns) Ordering Code
45 CY62138EV30LL-45BVXI 51-85149 36-ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free) Industrial
Package Diagrams
Package
Diagram Package Type
Operating
®
Range
0.25 C
8.00±0.10
A
0.55 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
B
6.00±0.10
36-ball VFBGA (6 x 8 x 1 mm) (51-85149)
0.21±0.05
0.10 C
0.75
5.25
8.00±0.10
2.625
A
B
0.15(4X)
BOTTOM VIEW
Ø0.05 M C
Ø0.25MCAB
Ø0.30±0.05(36X)
65
1.875
0.75
6.00±0.10
3.75
A1 CORNER
234
1
A
B
C
D
E
F
G
H
0.26 MAX.
SEATING PLANE
C
1.00 MAX
51-85149-*C
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semicond uctor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05577 Rev. *A Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herei n is su bject to change without notice. Cypress Semi con duct or Corpo ration assume s no resp onsib ility f or the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY62138EV30 2-Mbit (256K x 8) MoBL® Static RAM
Document Number: 38-05577
REV. ECN NO.
Date
** 237432 See ECN AJU New data sheet
*A 427817 See ECN NXR Removed 35 ns Speed Bin
Issue
Orig. of
Change Description of Change
Removed “L” version
Removed 32-pin TSOPII package from product Offering.
Changed ball C3 from DNU to NC.
Removed the redundant footnote on DNU.
Moved Product Portfolio from Page # 3 to Page #2.
Changed I
1.5 mA to 2 mA at f = 1 MHz
Changed I
Changed I
2.5 µA to 7 µA.
Changed V
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed V
Changed I
on Page # 4.
(Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
CC
(Typ) value from 12 mA to 15 mA at f = f
CC
and I
SB1
stabilization time in footnote #7 from 100 µs to 200 µs
CC
from 1.5V to 1V on Page# 4.
DR
from 1 µA to 3 µA in the Data Retention Characteristics table
CCDR
Corected tR in Data Retention Characteristics from 100 µs to t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Updated the Ordering Information table and replaced Package Name
OHA, tLZCE, tLZWE
HZOE, tHZCE, tHZWE
from 3 ns to 5 ns
LZOE
and t
SCE
from 20 ns to 25 ns
SD
from 25 ns to 35 ns
PWE
column with Package Diagram.
CY62138EV30
MoBL
=1/t
max
Typ. values from 0.7 µA to 1 µA and Max. values from
SB2
from 6 ns to 10 ns
from 15 ns to 18 ns
from 40 ns to 35 ns
AW
RC
RC
ns
®
Document #: 38-05577 Rev. *A Page 9 of 9
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