Cypress CY62138CV30, CY62138CV33, CY62138FV30, CY62138CV25 User Manual
CY62138FV30 MoBL
®
2-Mbit (256K x 8) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62138CV25/30/33
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
, CE2, and OE features
1
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Logic Block Diagram
Functional Description
[1]
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Place the device into standby
mode reducing power consumption when deselected (CE
HIGH or CE2 LOW).
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
specified on the address pins (A
through IO7) is then written into the location
0
through A17).
0
LOW and CE
1
To read from the device, take Chip Enable (CE1 LOW and CE
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE
) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
in a high impedance state when the device is deselected (CE
through IO7) are placed
0
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
LOW).
LOW and CE2 HIGH and WE
1
1
2
2
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
9
10
11
ROW DECODER
A
A
CE
1
CE
2
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
A
WE
OE
DATA IN DRIVERS
256K x 8
ARRAY
COLUMN DECODER
14
16
13
12
A
A15A
A
A
SENSE AMPS
POWER
DOWN
17
A
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-08029 Rev. *E Revised March 26, 2007
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CY62138FV30 MoBL
®
Pin Configuration
36-Ball VFBGA
A
A
1
0
IO
A
4
2
IO
5
V
SS
V
CC
IO
6
IO
OE
7
A
A
10
9
[2]
Top View
CE
2
WE
NC
NC
CE
1
A
11
32-Pin SOIC/TSOP II
Top Vi e w
A
A
3
A
4
A
5
A
17
A
16
A
12
A
6
A
IO
7
IO
V
V
IO
IO
A
15
A
A
13
8
CC
SS
14
A
B
0
C
1
D
E
F
2
G
3
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
12
0
IO
13
0
IO
1
14
IO
15
2
V
16
SS
V
CC
32
A
31
15
CE
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
A
A
A
A
OE
A
CE
IO
IO
IO
IO
IO
2
13
8
9
11
10
1
7
6
5
4
3
H
A
1
11
2
A
9
3
A
8
4
A
13
5
WE
6
CE
2
7
A
15
8
V
CC
9
A
17
A
10
16
A
11
14
A
12
12
A
13
7
A
14
6
15
A
5
16
A
4
TSOP I
Top V i e w
(not to scale)
32
OE
31
A
10
30
CE
1
29
IO
7
28
IO
6
27
IO
5
26
IO
4
25
IO
3
24
GND
IO
23
2
22
IO
1
IO
21
0
A
20
0
A
19
1
18
A
2
A
17
3
A
11
25
A
9
26
A
26
27
8
28
A
13
29
WE
30
CE
2
31
A
15
32
V
CC
A
1
17
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
7
A
5
8
A
4
STSOP
Top V iew
(not to scale)
24
OE
23
A
10
22
CE
1
21
IO
7
20
IO
6
19
IO
5
18
IO
4
17
IO
3
16
GND
IO
15
2
14
IO
1
IO
13
0
A
12
0
A
11
1
10
A
2
A
9
3
Product Portfolio
Power Dissipation
V
Product
Range (V)
CC
Min Typ
[3]
Max Typ
Speed
(ns)
Operating I
f = 1 MHz f = f
[3]
Max Typ
CY62138FV30LL 2.2 3.0 3.6 45 1.6 2.5 13 18 1 5
CC
(mA)
[3]
max
Max Typ
Standby I
[3]
SB2
(µA)
Max
Note
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, TA = 25°C.
Document #: 001-08029 Rev. *E Page 2 of 13
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CY62138FV30 MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
DC Input Voltage
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Power Applied...............................................55°C to +125°C
Supply Voltage to Ground
Potential........................................................... –0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
.......................................... –0.3V to 3.9V
CY62138FV30LL Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[7]
Output HIGH Voltage IOH = –0.1 mA 2.0 V
= –1.0 mA, V
I
OH
> 2.70V 2.4 V
CC
Output LOW Voltage IOL = 0.1 mA 0.4 V
= 2.1 mA, V
I
OL
Input HIGH Voltage V
Input LOW Voltage V
= 2.2V to 2.7V 1.8 V
CC
= 2.7V to 3.6V 2.2 V
V
CC
= 2.2V to 2.7V For BGA package –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
= 2.2V to 3.6V For other packages –0.3 0.6 V
V
CC
Input Leakage Current GND < VI < V
> 2.70V 0.4 V
CC
CC
Output Leakage Current GND < VO < VCC,
output disabled
VCC Operating Supply Current f = f
Automatic CE Power Down
Current CMOS Inputs
Automatic CE Power Down
Current CMOS Inputs
= 1/t
max
RC
f = 1 MHz 1.6 2.5
CE1 > V
VIN > V
f = f
f = 0 (OE
– 0.2V or CE2 < 0.2V,
CC
– 0.2V, V
CC
(address and data only),
max
, and WE), V
VCC = V
I
= 0 mA
OUT
CMOS levels
< 0.2V),
IN
= 3.60V
CC
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, V
= 3.60V
CC
[4, 5]
.......................................–0.3V to 3.9V
Product Range
Min Typ
–1 +1 µA
–1 +1 µA
CCmax
Ambient
Temperature
V
45 ns
[3]
Max
+ 0.3V V
CC
+ 0.3V V
CC
13 18 mA
15µA
15µA
CC
[6]
Unit
Capacitance (For all packages)
[8]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Notes
4. V
5. V
6. Full device AC operation assumes a 100 µs ramp time from 0 to V
7. Only chip enables (CE
8. Tested initially and after any design or process changes that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min)
= VCC+0.75V for pulse durations less than 20 ns.
IH(max)
Input Capacitance TA = 25°C, f = 1 MHz,
= V
V
CC
Output Capacitance 10 pF
and CE2) must be at CMOS level to meet the I
1
CC(typ.)
(min) and 200 µs wait time after V
CC
/ I
SB2
spec. Other inputs can be left floating.
CCDR
stabilization.
CC
10 pF
Document #: 001-08029 Rev. *E Page 3 of 13
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CY62138FV30 MoBL
®
Thermal Resistance
[8]
Parameter Description Test Conditions SOIC VFBGA TSOP II STSOP TSOP I Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still air, soldered on a 3 x 4.5
inch, two layer printed circuit
board
44.53 38.49 44.16 59.72 50.19 °C/W
24.05 17.66 11.97 15.38 14.59 °C/W
AC Test Loads and Waveforms
V
CC
OUTPUT
30 pF
R2
V
CC
GND
Rise Time = 1 V/ns
INCLUDING
R1
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
R
OUTPUT V
Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
ALL INPUT PULSES
10%
TH
90%
90%
10%
Fall Time = 1 V/ns
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
[8]
t
CDR
[9]
t
R
Data Retention Waveform
Notes:
9. Full device AC operation requires linear V
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
10. CE
VCC for Data Retention 1.5 V
[7]
Data Retention Current VCC = 1.5V,
CE
> VCC − 0.2V or CE2 < 0.2V,
1
V
> VCC − 0.2V or VIN < 0.2V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
[10]
DATA RETENTION MODE
V
ramp from V
CC
CC(min)
t
CDR
DR
to V
> 100 µs or stable at V
CC(min)
V
CC
CE
VDR> 1.5V
CC(min)
> 100 µs.
RC
V
CC(min)
t
R
[3]
Max Unit
14µA
ns
Document #: 001-08029 Rev. *E Page 4 of 13
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