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CY62138CV
Datasheet (CYPRESS)
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Datasheet CY62138CV25, CY62138CV30, CY62138CV33, CY62138CV Datasheet (CYPRESS)

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查询CY62138CV25供应商
Features
• Very high speed: 55 ns and 70 ns
—CY62138CV30: 2.7V–3.3V —CY62138CV33: 3.0V–3.6V —CY62138CV: 2.7V–3.6V
• Pin-compatible with CY62138V
• Ultra low active power —Typical active current: 1.5 mA @ f = 1 MHz —Typical active current: 5.5 mA @ f = f
speed)
• Low standby power
• Easy memory expansion with CE
features
, CE2, and OE
1
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 36-ball FBGA
Functional Description
[1]
The CY62138CV25/30/33 and CY62138CV are high-perfor­mance CMOS stati c RAMs org anize d as 256K word s by eig ht
max
(70-ns
CY62138CV25/30/33 MoBL
CY62138CV MoBL
® ®
2M (256K x 8) Static RAM
bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for provi ding More Batter y
(MoBL®) in portable applications. The device also has
Life™ an automatic power-down feature that significantly reduces power consumption by 80% when addr esses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE
LOW).
or CE
2
Writing to the device is accomplished by taking Chip Enable 1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
1
(CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the loc ation spe cified on the address pin s (A through A17).
Reading from the device is accomplished by taking Chip Enable 1 (CE Write Enable (WE) and Chip Enable 2 (CE2) HIGH. Under
) and Output Enable (O E) LOW while forcing
1
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O high-impedance state when the device is deselected (CE
through I/O7) are placed in a
0
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE See the truth table at the b ack of this data shee t for a complete
LOW, CE2 HIGH and WE LOW).
1
description of read and write modes.
HIGH
1
0
1
Logic Block Diagram
I/O I/O I/O I/O I/O I/O I/O I/O
0
1
2
3
4
5
6
7
ROW DECODER
Data in Drivers
256K x 8
ARRAY
COLUMN
DECODER
15
13
12
14
A
A
A
A
SENSE AMPS
POWER
DOWN
16
17
A
A
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
CE
1
CE
2
Note:
1. For best practice recommendations, please refer to the Cypress applic a tion note “System Design Guidelines” on http://www.cypress.com.
WE
OE
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-05200 Rev. *D Revised September 20, 2002
CY62138CV25/30/33 MoBL
CY62138CV MoBL
® ®
Pin
Configuration
[2, 3]
A
I/O
I/O
V
V
I/O
I/O
A
FBGA (Top View)
1
2
A
1
0
A
4
2
5
SS
CC
6
OE
7
A
10
9
3
CE
WE A
DNU
NC
CE
A
11
Maximum Ratings
(Above which the useful life may be impaired. For user guide­lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................55°C to +125°C
Supply Voltage to Ground Potential ... –0.5V V DC Voltage Applied to Outputs
in High-Z State DC Input Voltage
[4]
.....................................0.5V to VCC + 0.3V
[4]
.................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW) ............................ 20 mA
CCMAX
+ 0.5V
4
5
6
A
A
3
2
A
4
A
5
A
17
A
1
16
A
12
A
6
I/O
7
I/O
V
CC
V
SS
I/O
I/O
A
15
A
A
13
A
8
B
0
C
1
D
E
F
2
G
3
H
14
Stat ic Disc ha rge Voltage................................. ...... ....> 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ...................................................> 200 mA
Operating Range
Product Range
CY62138CV25 Industrial –40°C to +85°C 2.2V to 2.7V CY62138CV30 2.7V to 3.3V CY62138CV33 3.0V to 3.6V CY62138CV 2.7V to 3.6V
Ambient
Te mpe r ature T
A
V
CC
Product Portfolio
Power Dissipation
Operating, ICC (mA) Standby, I
Product
VCC Range (V)
[5]
Speed
Max. Typ.
(ns)
f = 1 MHz f = f
[5]
Max. Typ.
[5]
max
Max.
Typ.
[5]
CY62138CV25LL 2.2 2.5 2.7 55 1.5 3 7 15 2 10
70 1.5 3 5.5 12
CY62138CV30LL 2.7 3.0 3.3 55 1.5 3 7 15 2 10
70 1.5 3 5.5 12
CY62138CV33LL 3.0 3.3 3.6 55 1.5 3 7 15 5 15
70 1.5 3 5.5 12
CY62138CVLL 2.7 3.3 3.6 70 1.5 3 5.5 12 5 15
Notes:
2. NC pins are not connected to the die.
3. C3 (DNU) can be left as NC or V
4. V
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
to ensure proper application.
SS
= V
CC
CC(typ.)
, TA = 25°C.
Document #: 38-05200 Rev. *D Page 2 of 12
SB2
Max.Min. Typ.
(µA)
Electrical Characteristics Ov er the Op erat ing Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Output HIGH Voltage IOH = –0.1 mA VCC = 2.2V 2.0 2.0 V Output LOW Voltage IOL = 0.1 mA VCC = 2.2V 0.4 0.4 V Input HIGH Voltage 1.8 V
Input LOW Voltage –0.3 0.6 –0.3 0.6 V Input Leakage Current GND < VI < V Output Leakage
GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA
CC
Current VCC Operating Supply
Current
Automatic CE Power-down Current — CMOS Inputs
Automatic CE Power-down Current — CMOS Inputs
f = f f = 1 MHz 1.5 3 1.5 3
MAX
= 1/t
RC
VCC = 2.7V I
OUT
CMOS Levels
CE1 > VCC – 0.2V or CE2 < 0.2V V
> VCC – 0.2V or VIN < 0.2V, f =
IN
f
(Address and Data Only), f = 0
max
(OE
, WE)
CE1 > VCC – 0.2V or CE2 < 0.2V
> VCC − 0.2V or VIN < 0.2V , f = 0, V
V
IN
= 2.7V
Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 2.4 V Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 0.4 V Input HIGH Voltage 2.2 V
Input LOW Voltage –0.3 0.8 –0.3 0.8 V Input Leakage Current GND < VI < V Output Leakage
GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA
CC
Current VCC Operating Supply
Current
Automatic CE Power-down Current — CMOS Inputs
Automatic CE Power-down Current — CMOS Inputs
f = f f = 1 MHz 1.5 3 1.5 3
MAX
= 1/t
RC
VCC = 3.3V I
OUT
CMOS Levels
CE1 > VCC – 0.2V or CE2 < 0.2V V
> VCC – 0.2V or VIN < 0.2V, f =
IN
f
(Address and Data Only), f = 0
max
(OE
, WE)
CE1 > VCC – 0.2V or CE2 < 0.2V, VIN
VCC − 0.2V or VIN < 0.2V , f = 0,
> VCC=3.3V
= 0 mA
= 0 mA
CY62138CV25/30/33 MoBL
CY62138CV MoBL
CY62138CV25-55 CY62138CV25-70
[5]
Max. Min. Typ.
+
1.8 V
CC
0.3V
–1 +1 –1 +1 µA
7 15 5.5 12 mA
2 10 2 10 µA
CC
CY62138CV30-55 CY62138CV30-70
[5]
Max. Min. Typ.
+
2.2 V
CC
0.3V
–1 +1 –1 +1 µA
7 15 5.5 12 mA
2 10 2 10 µA
[5]
[5]
Max.
CC
0.3V
Max.
CC
0.3V
® ®
UnitMin. Typ.
+
V
UnitMin. Typ.
+
V
Document #: 38-05200 Rev. *D Page 3 of 12
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Electrical Characteristics Ov er the Op erat ing Range
CY62138CV33-55
Parameter Description Test Conditions
V
OH
Output HIGH Voltage IOH = –1.0 mA VCC = 3.0V 2.4 2.4 V
[5]
Max. Min. Typ.
VCC = 2.7V 2.4 V
V
OL
Output LOW Voltage IOL = 2.1 mA VCC = 3.0V 0.4 0.4 V
VCC = 2.7V 0.4 V
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Capacitance
Input HIGH Voltage 2.2 V
0.3V Input LOW Voltage –0.3 0.8 –0.3 0.8 V Input Leakage Current GND < VI < V Output Leakage
GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA
CC
–1 +1 –1 +1 µA
Current VCC Operating Supply
Current
Automatic CE Power-down Current— CMOS Inputs
Automatic CE Power-down Current— CMOS Inputs
[6]
f = f f = 1 MHz 1.5 3 1.5 3
CE1 > VCC – 0.2V or CE2 < 0.2V V f = f f = 0 (OE
= 1/t
MAX
> VCC – 0.2V or VIN < 0.2V,
IN
max
RC
(Address and Data Only),
VCC = 3.6V
= 0 mA
I
OUT
CMOS Levels
,WE)
7 15 5.5 12 mA
5 15 5 15 µA
CE1 > VCC – 0.2V or CE2 < 0.2V VIN > VCC − 0.2V or VIN < 0.2V,
CC
= 3.6V
f = 0, V
Parameter Description T est Conditions Max. Unit
C
IN
C
OUT
Thermal Resistance
Input Capacitance TA = 25°C, f = 1 MHz, VCC = V
CC(typ.)
Output Capaci tance 8 pF
Parameter Description T est Condit ions BGA Unit
Θ
JA
Θ
JC
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
[6]
Still A ir, soldered on a 3 x 4.5 inch, two-l aye r pri nte d circuit board
[6]
CY62138CV33-70
CY62138CV-70
+
2.2 V
CC
6 pF
[5]
Max.
CC
0.3V
55 °C/W
16 °C/W
® ®
UnitMin. Typ.
+
V
AC Test Loads and Waveforms
30 pF
SCOPE
R1
VCC Typ
R2
Equivalent to: THÉ VENIN EQUIVALENT
OUTPUT V
GND
Rise Time: 1 V/ns
10%
R
TH
ALL INPUT PULSES
90%
TH
90%
10%
Fall time: 1 V/ns
V
CC
OUTPUT
INCLUDING
JIG AND
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05200 Rev. *D Page 4 of 12
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Parameters 2.5V 3.0V 3.3V Unit
R1 16600 1105 1216 Ω R2 15400 1550 1374 Ω
R
TH
V
TH
Data Retention Characte ristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
V
DR
I
CCDR
t
CDR
[7]
t
R
[6]
VCC for Data Retention 1.5 V Data Retention Current VCC = 1.5V
Chip Deselect to Data Retention Time
Operation Recovery Time t
Data Retention Waveform
V
CC
CE1
or
CE
2
8000 645 645 Ω
1.20 1.75 1.75 V
[5]
1 6 µA
CE
> VCC – 0.2V or CE2 < 0.2V
1
V
> VCC − 0.2V or VIN < 0.2V
IN
0 ns
RC
DATA RETENTION MODE
V
CC(min.)
t
CDR
VDR> 1.5 V
V
CC(min.)
t
R
Max. Unit
CC(max.)
ns
® ®
V
Switching Characteristics Over the Operating Range
[8]
55 ns 70 ns
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
Notes:
7. Full-device AC operation requires linear V
8. T est conditions assume signal transition time of 5 ns or less, timing reference levels of V specified I
9. At any given temperature and voltage condition, t
10. t
11. The internal write time of the memory is defined by the overlap of WE signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
HZOE
, t
[11]
and 30-pF load capacitance.
OL/IOH
, and t
HZCE
HZWE
Read Cycle Time 55 70 ns Address to Data Valid 55 70 ns Data Hold from Address Change 10 10 ns CE1 LOW and CE2 HIGH to Data Valid 55 70 ns OE LOW to Data Valid 25 35 ns OE LOW to Low-Z OE HIGH to High-Z CE1 LOW and CE2 HIGH to Low-Z CE1 HIGH or CE2 LOW to High-Z
[9]
[9, 10]
[9]
[9, 10]
5 5 ns
20 25 ns
10 10 ns
20 25 ns CE1 LOW and CE2 HIGH to Power-up 0 0 ns CE1 HIGH or CE2 LOW to Power-down 55 70 ns
Write Cycle Time 55 70 ns CE1 LOW and CE2 HIGH to Write End 45 60 ns
ramp from V
CC
transitions are measured when the outputs enter a high-impedance state.
HZCE
to V
DR
CC(min.)
is less than t
> 100 µs or stable at V
, t
LZCE
HZOE
, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
CC(typ.)
is less than t
LZOE
> 100 µs.
CC(min.)
/2, input pulse levels of 0 to V
, and t
is less than t
HZWE
, and output loading of the
CC(typ.)
for any given device.
LZWE
UnitMin. Max. Min. Max.
Document #: 38-05200 Rev. *D Page 5 of 12
CY62138CV25/30/33 MoBL
CY62138CV MoBL
® ®
Switching Characteristics Over the Operating Range
Parameter Description
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Address Set-up to Write End 45 60 ns Address Hold from Write End 0 0 ns Address Set-up to Write Start 0 0 ns WE Pulse Width 40 45 ns Data Set-up to Write End 25 30 ns Data Hold from Write End 0 0 ns WE LOW to High-Z WE HIGH to Low-Z
[9, 10] [9]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
ADDRESS
t
OHA
DATA OUT PREVIOUS
DATA VALID
[12, 13]
t
AA
[8]
(continued)
t
RC
55 ns 70 ns
UnitMin. Max. Min. Max.
20 25 ns
10 10 ns
DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
1
CE
2
OE
DATA OUT
V
CC
SUPPLY
CURRENT
Notes:
12. Device is continuously selected. OE is HIGH for read cycle.
13. WE
14. Address valid prior to or coincident with CE
HIGH IMPEDANCE
t
LZCE
t
PU
, CE1 = VIL, CE2=VIH.
[13, 14]
t
RC
t
ACE
t
DOE
t
LZOE
50%
transition LOW and CE2 transition HIGH.
1
DATA VALID
t
HZOE
t
HZCE
HIGH
IMPEDANCE
t
PD
50%
I
CC
I
SB
Document #: 38-05200 Rev. *D Page 6 of 12
Switching Waveforms (continued)
CY62138CV25/30/33 MoBL
CY62138CV MoBL
® ®
Write Cycle No. 1 (WE Co ntrolled)
[11, 15 , 17]
ADDRESS
CE
1
CE
2
t
SA
WE
OE
DATA I/O
NOTE
16
t
HZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)
t
AW
[11, 15 , 17]
t
SCE
t
WC
t
PWE
t
SD
DATAINVALID
t
HA
t
HD
t
WC
ADDRESS
CE
1
t
CE
2
SA
t
AW
t
PWE
WE
OE
DATA I/O
Notes:
15. Data I/O is high impedance if OE
16. During this period, the I/Os are in output state and input signals should not be applied.
17. If CE
goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.
1
= VIH.
t
SCE
t
SD
DATAIN VALID
t
HA
t
HD
Document #: 38-05200 Rev. *D Page 7 of 12
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
[17]
t
SCE
t
WC
CY62138CV25/30/33 MoBL
CY62138CV MoBL
® ®
WE
DATAI/O
NOTE 16
t
AW
t
SA
t
HZWE
t
PWE
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
Document #: 38-05200 Rev. *D Page 8 of 12
Typical DC and AC Parameters
CY62138CV25/30/33 MoBL
CY62138CV MoBL
® ®
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = V
Operating Current vs. Supply Voltage
14.0
12.0
10.0 MoBL
(mA)
8.0
CC
I
6.0
4.0
2.0
0.0
2.2
2.5
2.7
SUPPLY VOLT AGE (V)
(f = f
max
55 ns)
(f = f
max
70 ns)
(f = 1MHz)
14.0
12.0
10.0 MoBL
(mA)
,
8.0
CC
I
6.0
,
4.0
2.0
0.0
2.7
SUPPLY VOLTAGE (V)
3.0
(f = f
55 ns)
(f = f
70 ns)
(f = 1MHz)
3.3
14.0
12.0
10.0 MoBL
(mA)
,
max
max
8.0
CC
I
6.0
,
4.0
2.0
0.0
3.0
SUPPLY VOLTAGE (V)
3.3
(f = f
55 ns)
(f = f
70 ns)
(f = 1MHz)
3.6
max
max
Standby Current vs. Supply Voltage
12.0
10.0 MoBL
8.0
SB (µA)
I
6.0
4.0
2.0 0
2.2
2.5
SUPPLY VOLTAGE (V)
2.7
12.0
10.0 MoBL
8.0
SB (µA)
I
6.0
4.0
2.0 0
3.0
2.7
SUPPLY VOLTAGE (V)
3.3
12.0 MoBL
10.0
8.0
SB (µA)
I
6.0
4.0
2.0 0
3.3
3.0
SUPPLY VOLT AGE (V)
Access Time vs. Supply Voltage
CC(typ.)
14.0
12.0
10.0 MoBL
(mA)
,
8.0
CC
I
6.0
,
4.0
2.0
0.0
2.7
SUPPLY VOLTAGE (V)
12.0
10.0
8.0
SB (µA)
I
6.0
4.0
2.0
3.6 SUPPLY VOLTAGE (V)
, TA = 25°C)
MoBL
0
2.7
3.3
(f = f
55 ns)
(f = f
70 ns)
(f = 1MHz)
3.6
3.3
max
max
3.6
, ,
60
MoBL
50 40 30
AA (ns)
20
T
10 0
2.2
2.5
2.7
SUPPLY VOLTAGE (V)
60
MoBL MoBL
50 40 30
AA (ns)
20
T
T
10 0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
60 50 40 30
AA (ns)
20 10
0
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
60
MoBL
50 40 30
AA (ns)
20
T
10 0
2.7
3.3
SUPPLY VOLTAGE (V)
3.6
Truth Table
CE
Document #: 38-05200 Rev. *D Page 9 of 12
CE
1
WE OE Inputs/Outputs Mode Power
2
H X X X High-Z Deselect/Power-down Standby (ISB) X L X X High-Z Deselect/Power-down Standby (ISB) L H H L Data Out (I/O0-I/O7) Read Active (ICC) L H H H High-Z Output Disabled Active (Icc) L H L X Data in (I/O0-I/O7) Write Active (Icc)
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Ordering Information
Speed
(ns) Ordering Code
70 CY62138CV25LL-70BAI 2.2–2.7 BA36A 36-ball Fin e Pitch BGA (7 mm x 7 mm x 1.2 mm) Industrial
CY62138CV25LL-70BVI 2.2–2.7 BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62138CV30LL-70BAI 2.7–3.3 BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) CY62138CV30LL-70BVI 2.7–3.3 BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62138CV33LL-70BAI 3.0–3.6 BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) CY62138CV33LL-70BVI 3.0–3.6 BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62138CVLL-70BAI 2.7–3.6 BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 m m) CY62138CVLL-70BVI 2.7–3.6 BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
55 CY62138CV25LL-55BAI 2.2–2.7 BA36A 36-ball Fin e Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62138CV25LL-55BVI 2.2–2.7 BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62138CV30LL-55BAI 2.7–3.3 BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) CY62138CV30LL-55BVI 2.7–3.3 BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62138CV33LL-55BAI 3.0–3.6 BA36A 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) CY62138CV33LL-55BVI 3.0–3.6 BV36A 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
Voltage
Range (V)
Package
Name Package Type
Operating
® ®
Range
Package Diagrams
36-ball FBGA (7 x 7 x 1.2 mm) BA36A
51-85099-*C
Document #: 38-05200 Rev. *D Page 10 of 12
Package Diagrams (continued)
CY62138CV25/30/33 MoBL
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
CY62138CV MoBL
® ®
51-85149-*A
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05200 Rev. *D P age 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize its products for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62138CV25/30/33 MoBL
CY62138CV MoBL
Document History Page
Document Title: CY62138CV25 /30/33 MoBL®/CY62138CV MoBL® 2M (256K x 8) Static RAM Document Number: 38-05200
REV. ECN NO. Issue Date Orig. of
Change
** 112381 02/19/02 GAV New Data Sheet (advance information)
*A 114024 04/25/02 JUI Added BV package diagram
Changed from Advance Information to Preliminary
*B 117062 07/12/02 MGN Added Second Chip Enable
Changed from Preliminary to Final
*C 118123 09/09/02 MGN Added new part number: CY62138CV with wider voltage (2.7V – 3.6V)
= 55 ns, improved t
For T
AA
= 70 ns, improved t
For T
AA
= 70 ns, improved t
For T
AA
*D 118760 09/23/02 MGN Improved Typ. I
Improved Max I
= 55 ns, improved t
For T
AA
Changed upper spec. for Supply Voltage to Ground Potential to V
CC CC
0.5V. Changed upper sp ec for DC Voltage Applied to Oupu t s in H i gh-Z State and DC Input Voltage to V
Description of Change
min. from 45 ns to 40 ns
PWE
min. from 60 ns to 45 ns
PWE
min. from 5 ns to 10 ns
LZWE
spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns). spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns).
min. from 5 ns to 10 ns.
LZWE
+ 0.3V.
CC
CCMAX
® ®
+
Document #: 38-05200 Rev. *D Page 12 of 12
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