CY62137FV30 MoBL
®
2-Mbit (128K x 16) Static RAM
Features
128K x 16
RAM Array
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A12A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO8–IO
15
CE
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
BHE
BLE
CE
POWER DOWN
CIRCUIT
Logic Block Diagram
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Wide voltage range: 2.20V–3.60V
■ Pin compatible with CY62137CV/CV25/CV30/CV33,
CY62137V, and CY62137EV30
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 5 μA (Industrial)
■ Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Byte power down feature
■ Available in Pb free 48-Ball VFBGA and 44-pin TSOP II
package
Functional Description
The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE
BHE
are HIGH). The input and output pins (IO0 through IO15) are
HIGH or both BLE and
placed in a high impedance state in the following conditions:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE
(WE
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
specified on the address pins (A
Enable (BHE
through IO7) is written into the location
0
) is LOW, then data from IO pins (IO8 through IO15)
through A16). If Byte High
0
) and Write Enable
is written into the location specified on the address pins (A
through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE
Byte Low Enable (BLE
location specified by the address pins appear on IO
Byte High Enable (BHE
appears on IO
complete description of read and write modes.
) LOW, while forcing the Write Enable (WE) HIGH. If
) is LOW, then data from the memory
to IO7. If
) is LOW, then data from memory
to IO15. See the “Truth Table” on page 9 for a
8
0
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-07141 Rev. *F Revised January 2, 2008
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CY62137FV30 MoBL
®
Product Portfolio
WE
A
11
A
10
A
6
A
0
A
3
CE
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
NC
NC
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC
NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
16
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Power Dissipation
Product Range
VCC Range (V)
Min Typ
Speed
[1]
Max Typ
(ns)
Operating ICC (mA)
f = 1MHz f = f
[1]
Max Typ
[1]
max
Max Typ
Standby I
(μA)
[1]
Max
CY62137FV30LL Ind’l/Auto-A 2.2V 3.0V 3.6V 45 1.6 2.5 13 18 1 5
Auto-E 2.2V 3.0V 3.6V 55 2 3 15 25 1 20
Pin Configuration
SB2
Figure 1. 48-Ball VFBGA Pinout
[2, 3]
Figure 2. 44-Pin TSOP II
[2]
Document Number: 001-07141 Rev. *F Page 2 of 12
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CY62137FV30 MoBL
®
Maximum Ratings
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max)=VCC
+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
7. Only chip enable (CE
) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I
SB2
/ I
CCDR
specification. Other inputs can be left floating.
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ...........................................................-0.3V to 3.9V
DC Voltage Applied to Outputs
in High Z state
[4, 5]
.................................. .. ... .....-0.3V to 3.9V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[7]
Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 2.0 V
VCC < 3.6 IOH = –1.0 mA 2.4 2.4 V
2.7 <
Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 0.4 V
VCC < 3.6 IOL = 2.1mA 0.4 0.4 V
2.7 <
Input HIGH Volt age 2.2 < VCC < 2.7 1.8 V
VCC < 3.6 2.2 V
2.7 <
Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 –0.3 0.6 V
VCC < 3.6 –0.3 0.8 –0.3 0.8 V
2.7 <
Input Leakage Current GND < VI < V
Output Leakage
GND < VO < VCC, Output disabled –1 +1 –4 +4 μA
CC
Current
VCC Operating Supply
Current
Automatic CE Power
Down Current – CMOS
Inputs
Automatic CE Power
Down Current – CMOS
Inputs
f = f
= 1/t
max
RC
f = 1 MHz 1.6 2.5 2 3
CE
> VCC – 0.2V,
V
> V
IN
f = f
f = 0 (OE
CE
V
IN
f = 0, V
– 0.2V, V
CC
(address and data only),
max
, WE, BHE, and BLE), V
> VCC – 0.2V ,
> VCC – 0.2V or VIN < 0.2V,
= 3.60V
CC
VCC = V
I
OUT
CMOS levels
< 0.2V
IN
DC Input Voltage
[4, 5]
.................................. .....–0.3V to 3.9V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch up Current ....................................................> 200 mA
Operating Range
Device Range
CY62137FV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
Auto-E –40°C to +125°C
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Typ
[1]
Max Min Typ
CC
CC
–1 +1 –4 +4 μA
CC(max)
= 0 mA
13 18 15 25 mA
15 120μA
= 3.60V
CC
15 120μA
Ambient
Temperature
[1]
+ 0.3 1.8 V
+ 0.3 2.2 V
Max
CC
CC
[6]
V
CC
Unit
+ 0.3 V
+ 0.3 V
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Document Number: 001-07141 Rev. *F Page 3 of 12
Input Capacitance TA = 25°C, f = 1 MHz,
V
Output Capacitance 10 pF
CC
= V
CC(typ)
10 pF
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CY62137FV30 MoBL
®
Thermal Resistance
VCC
V
CC
OUTPUT
R2
30 pF
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
INCLUDING
JIG AND
SCOPE
V
CC(min)
V
CC(min)
t
CDR
VDR> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE or
BHE
.BLE
Notes
8. T ested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
10.BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Tested initially and after any design or process chang es that may affect these parameters.
Parameter Description Test Conditions VFBGA TSOP II Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
75 77 °C/W
10 13 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveform
Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
VCC for Data Retention 1.5 V
[7]
Data Retention Current V
= 1.5V, CE > VCC - 0.2V ,
CC
VIN > VCC - 0.2V or VIN < 0.2V
[8]
t
CDR
t
R
[9]
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
Data Retention Waveform
Figure 4. Data Retention Waveform
Document Number: 001-07141 Rev. *F Page 4 of 12
[1]
Max Unit
Ind’l/Auto-A 4 μA
Auto-E 12
RC
[10]
ns
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CY62137FV30 MoBL
®
Switching Characteristics
Notes
11.Test conditions for all parameters, othe r than tri-state paramete rs, assume signal transition time o f 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.
12.AC timing parameters are subject to byte enable signals (BHE
or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarif ication.
13.At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
14.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
15.If both byte enables are toggled together, this value is 10 ns.
16.The internal write time of the memory is defined by the overlap of WE
, CE = VIL, BHE and/or BLE = VIL. All signals are ACTIVE to initiate a write and any of these
signals terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the wr ite.
Over the Operating Range
[11, 12]
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
Read Cycle Time 45 55 ns
Address to Data Valid 45 55 ns
Data Hold From Address Change 10 10 ns
CE LOW to Data Valid
OE LOW to Data Va lid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[13]
[13, 14]
[13]
[13, 14]
CE LOW to Power Up
CE HIGH to Power Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to High Z
[16]
[13, 15]
[13, 14]
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Unit
Min Max Min Max
45 55 ns
22 25 ns
55ns
18 20 ns
10 10 ns
18 20 ns
00ns
45 55 ns
45 55 ns
510ns
18 20 ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Document Number: 001-07141 Rev. *F Page 5 of 12
Write Cycle Time 45 55 ns
CE LOW to Write End
35 40 ns
Address Setup to Write End 35 40 ns
Address Hold from Write End 0 0 ns
Address Setup to Write Start 0 0 ns
WE Pulse Width
BLE/BHE LOW to Write End
35 40 ns
35 40 ns
Data Setup to Write End 25 25 ns
Data Hold From Write End 0 0 ns
WE LOW to High Z
WE HIGH to Low Z
[13, 14]
[13]
10 10 ns
18 20 ns
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CY62137FV30 MoBL
®
Switching Waveforms
PREVIOUS DATA VALID DA TA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE
/BLE
ADDRESS
Notes
17.The device is continuously selected. OE
, CE = VIL, BHE and/or BLE = VIL.
18.WE
is HIGH for read cycle.
19.Address valid before or similar to CE
and BHE, BLE transition LOW.
Figure 5. Read Cycle 1: Address Transition Controlled
[17, 18]
Figure 6. Read Cycle 2: OE Controlled
[18, 19]
Document Number: 001-07141 Rev. *F Page 6 of 12
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CY62137FV30 MoBL
®
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
t
HZOE
DATA
IN
NOTE 22
t
BW
t
SCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
t
BW
t
SA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 22
Notes
20.Data IO is high impedance if OE
= VIH.
21.If CE
goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
22.During this period, the IOs are in output state. Do not apply input signals.
Figure 7. Write Cycle 1: WE
Controlled
[16, 20, 21]
Figure 8. Write Cycle 2: CE Controlled
[16, 20, 21]
Document Number: 001-07141 Rev. *F Page 7 of 12
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CY62137FV30 MoBL
®
Switching Waveforms (continued)
DATAIN
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 22
CE
ADDRESS
WE
DATA IO
BHE
/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
DATA
IN
t
BW
t
SCE
t
PWE
t
HZWE
t
LZWE
NOTE 22
DATA IO
ADDRESS
CE
WE
BHE/BLE
Figure 9. Write Cycle 3: WE
Controlled, OE LOW
[21]
[21]
Figure 10. Write Cycle 4: BHE/BLE Controlled, OE LOW
Document Number: 001-07141 Rev. *F Page 8 of 12
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CY62137FV30 MoBL
®
T ruth Table
CE WE OE BHE BLE Inputs or Outputs Mode Power
HXXXXHigh Z Deselect or Power Down Standby (I
X X X H H High Z Deselect or Power Down Standby (ISB)
L H L L L Data Out (IO0–IO15)Read Active (I
LHLHLData Out (IO0–IO7);
–IO
IO
L H L L H Data Out (IO
IO
in High Z
8
15
–IO7 in High Z
0
8
–IO15);
Read Active (I
Read Active (I
L H H L L High Z Output Disabled Active (I
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (IO
L L X H L Data In (IO0–IO7);
IO
–IO
8
L L X L H Data In (IO
IO
–IO7 in High Z
0
–IO15) Write Active (ICC)
0
Write Active (I
in High Z
15
–IO15);
8
Write Active (I
CC
CC
CC
CC
CC
CC
SB
)
)
)
)
)
)
)
Document Number: 001-07141 Rev. *F Page 9 of 12
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CY62137FV30 MoBL
®
Ordering Information
A
1
A1 CORNER
0.75
0.75
Ø0.30±0.05(48X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.21±0.05
1.00 MAX
C
SEATING PLANE
0.55 MAX.
0.25 C
0.10 C
A1 CORNER
TOP VIEW
BOTTOM VIEW
234
3.75
5.25
B
C
D
E
F
G
H
65
465231
D
H
F
G
E
C
B
A
6.00±0.10
8.00±0.10
A
8.00±0.10
6.00±0.10
B
1.875
2.625
0.26 MAX.
51-85150-*D
Speed
(ns) Ordering Code
45 CY62137FV30LL-45BVI 51-85150 48-Ball VFBGA Industrial
CY62137FV30LL-45BVXI 48-Ball VFBGA (Pb-free)
CY62137FV30LL-45ZSXI 51-85087 44-Pin TSOP II (Pb-free)
45 CY62137FV30LL-45ZSXA 51-85087 44-Pin TSOP II (Pb-free) Automotive-A
55 CY62137FV30LL-55ZSXE 51-85087 44-Pin TSOP II (Pb-free) Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package Diagram
Package Type
Operating
Range
Package Diagram
Figure 11. 48-Ball VFBGA (6 x 8 x 1 mm)
Document Number: 001-07141 Rev. *F Page 10 of 12
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CY62137FV30 MoBL
®
Package Diagram (continued)
51-85087-*A
Figure 12. 44-Pin TSOP II
Document Number: 001-07141 Rev. *F Page 1 1 of 12
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CY62137FV30 MoBL
®
Document History Page
Document Title: CY62137FV30 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 001-07141
REV. ECN NO.
Issue
Date
** 449438 See ECN NXR New datasheet
*A 464509 See ECN NXR Changed the I
*B 566724 See ECN NXR Converted from prelimina r y to final
*C 869500 See ECN VKN Added Automotive-A and Automotive-E information
*D 901800 See ECN VKN Added footnote 9 related to I
*E 1371124 See ECN VKN/AESA Converted Automotive information from preliminary to final
*F 1875374 See ECN VKN/AESA Added -45BVI part in the Ordering Information table
Orig. of
Change Description of Change
value from 1.0 μA to 0.5 μA
Changed the I
Changed the I
2.5 mA to 2.25 mA for f=1 MHz test condition
Changed the I
20 mA to 18 mA for f=1 MHz test condition
Changed the I
2.5 μA
Changed the I
Changed the I
Changed the I
Changed the I
4 μA
SB2(typ)
SB2(max)
CC(typ)
CC(typ)
CCDR(typ)
CC(max)
SB2(typ)
SB2(max)
CCDR(typ)
value from 4 μA to 2.5 μA
value from 2 mA to 1.6 mA and I
value from 15 mA to 13 mA and I
value from 0.7 μA to 0.5 μA and I
value from 2.25 mA to 2.5 mA for test condition f=1 MHz
value from 0.5 μA to 1 μA
value from 2.5 μA to 5 μA
value from 0.5 μA to 1 μA and I
Updated Ordering Information Table
Added footnote 13 related to t
Made footnote 14 applicable to AC parameters from t
Changed I
Changed I
min spec from –1 μA to –4 μA and I
IX
min spec from –1 μA to –4 μA and I
OZ
ACE
SB2
and I
CCDR
max spec from +1 μA to +4 μA
IX
max spec from +1 μA to +4 μA
OZ
CC(max)
CC(max)
CCDR(max)
CCDR(max)
ACE
value from
value from
value from 3 μA to
value from 2.5 μA to
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life sa vin g, critical control or safety applicati ons, un l ess p ur suant to an express written agreement w i th Cy press. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States co pyright la ws and inte rnatio na l tre aty prov isi ons. Cyp ress he reby g rant s to lice nsee a p erson al, no n-ex clusi ve, non-tra nsferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpo se of creating custom sof tware and or firm ware in support of licen see product to be use d only in conjunction with a Cypress
integrated circuit as specified in th e applicable agreement. Any reproductio n, modification, translation, co mpilation, o r representati on of this Sour ce Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED T O, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the ap plicati on or u se o f any pr oduct o r circui t descri bed h erein. Cypr ess does not aut horize it s product s for use a s critical compo nent s in life-support systems whe re
a malfunction or failure may reasonab ly be expected to resu lt in significant injury t o the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-07141 Rev. *F Revised January 2, 2008 Page 12 of 12
MoBL is a registered trademark and More Bat tery Life is a trademark of Cypress Semiconductor . All product and company na mes mentioned in this document are the trademarks of their respective holders.
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