Cypress CY62137FV30 User Manual
CY62137FV30 MoBL
®
2-Mbit (128K x 16) Static RAM
Features
128K x 16
RAM Array
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A12A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO8–IO
15
CE
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
BHE
BLE
CE
POWER DOWN
CIRCUIT
Logic Block Diagram
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Wide voltage range: 2.20V–3.60V
■ Pin compatible with CY62137CV/CV25/CV30/CV33,
CY62137V, and CY62137EV30
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 5 μA (Industrial)
■ Ultra low active power
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Byte power down feature
■ Available in Pb free 48-Ball VFBGA and 44-pin TSOP II
package
Functional Description
The CY62137FV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (CE
BHE
are HIGH). The input and output pins (IO0 through IO15) are
HIGH or both BLE and
placed in a high impedance state in the following conditions:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE LOW and WE LOW)
Write to the device by taking Chip Enable (CE
(WE
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
specified on the address pins (A
Enable (BHE
through IO7) is written into the location
0
) is LOW, then data from IO pins (IO8 through IO15)
through A16). If Byte High
0
) and Write Enable
is written into the location specified on the address pins (A
through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE
Byte Low Enable (BLE
location specified by the address pins appear on IO
Byte High Enable (BHE
appears on IO
complete description of read and write modes.
) LOW, while forcing the Write Enable (WE) HIGH. If
) is LOW, then data from the memory
to IO7. If
) is LOW, then data from memory
to IO15. See the “Truth Table” on page 9 for a
8
0
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-07141 Rev. *F Revised January 2, 2008
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CY62137FV30 MoBL
®
Product Portfolio
WE
A
11
A
10
A
6
A
0
A
3
CE
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
A
7
IO
0
BHE
NC
NC
A
2
A
1
BLE
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC
NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
16
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Power Dissipation
Product Range
VCC Range (V)
Min Typ
Speed
[1]
Max Typ
(ns)
Operating ICC (mA)
f = 1MHz f = f
[1]
Max Typ
[1]
max
Max Typ
Standby I
(μA)
[1]
Max
CY62137FV30LL Ind’l/Auto-A 2.2V 3.0V 3.6V 45 1.6 2.5 13 18 1 5
Auto-E 2.2V 3.0V 3.6V 55 2 3 15 25 1 20
Pin Configuration
SB2
Figure 1. 48-Ball VFBGA Pinout
[2, 3]
Figure 2. 44-Pin TSOP II
[2]
Document Number: 001-07141 Rev. *F Page 2 of 12
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CY62137FV30 MoBL
®
Maximum Ratings
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max)=VCC
+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
7. Only chip enable (CE
) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I
SB2
/ I
CCDR
specification. Other inputs can be left floating.
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ...........................................................-0.3V to 3.9V
DC Voltage Applied to Outputs
in High Z state
[4, 5]
.................................. .. ... .....-0.3V to 3.9V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[7]
Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 2.0 V
VCC < 3.6 IOH = –1.0 mA 2.4 2.4 V
2.7 <
Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 0.4 V
VCC < 3.6 IOL = 2.1mA 0.4 0.4 V
2.7 <
Input HIGH Volt age 2.2 < VCC < 2.7 1.8 V
VCC < 3.6 2.2 V
2.7 <
Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 –0.3 0.6 V
VCC < 3.6 –0.3 0.8 –0.3 0.8 V
2.7 <
Input Leakage Current GND < VI < V
Output Leakage
GND < VO < VCC, Output disabled –1 +1 –4 +4 μA
CC
Current
VCC Operating Supply
Current
Automatic CE Power
Down Current – CMOS
Inputs
Automatic CE Power
Down Current – CMOS
Inputs
f = f
= 1/t
max
RC
f = 1 MHz 1.6 2.5 2 3
CE
> VCC – 0.2V,
V
> V
IN
f = f
f = 0 (OE
CE
V
IN
f = 0, V
– 0.2V, V
CC
(address and data only),
max
, WE, BHE, and BLE), V
> VCC – 0.2V ,
> VCC – 0.2V or VIN < 0.2V,
= 3.60V
CC
VCC = V
I
OUT
CMOS levels
< 0.2V
IN
DC Input Voltage
[4, 5]
.................................. .....–0.3V to 3.9V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch up Current ....................................................> 200 mA
Operating Range
Device Range
CY62137FV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
Auto-E –40°C to +125°C
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Typ
[1]
Max Min Typ
CC
CC
–1 +1 –4 +4 μA
CC(max)
= 0 mA
13 18 15 25 mA
15 120μA
= 3.60V
CC
15 120μA
Ambient
Temperature
[1]
+ 0.3 1.8 V
+ 0.3 2.2 V
Max
CC
CC
[6]
V
CC
Unit
+ 0.3 V
+ 0.3 V
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Document Number: 001-07141 Rev. *F Page 3 of 12
Input Capacitance TA = 25°C, f = 1 MHz,
V
Output Capacitance 10 pF
CC
= V
CC(typ)
10 pF
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CY62137FV30 MoBL
®
Thermal Resistance
VCC
V
CC
OUTPUT
R2
30 pF
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
INCLUDING
JIG AND
SCOPE
V
CC(min)
V
CC(min)
t
CDR
VDR> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE or
BHE
.BLE
Notes
8. T ested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
10.BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Tested initially and after any design or process chang es that may affect these parameters.
Parameter Description Test Conditions VFBGA TSOP II Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
75 77 °C/W
10 13 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveform
Parameters 2.5V (2.2V to 2.7V) 3.0V (2.7V to 3.6V) Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
V
DR
I
CCDR
VCC for Data Retention 1.5 V
[7]
Data Retention Current V
= 1.5V, CE > VCC - 0.2V ,
CC
VIN > VCC - 0.2V or VIN < 0.2V
[8]
t
CDR
t
R
[9]
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
Data Retention Waveform
Figure 4. Data Retention Waveform
Document Number: 001-07141 Rev. *F Page 4 of 12
[1]
Max Unit
Ind’l/Auto-A 4 μA
Auto-E 12
RC
[10]
ns
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