Logic Block Di
CY62137EV30
MoBL
®
2-Mbit (128K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62137CV30
• Ultra-low standby power
— Typical standby current: 1
µA
— Maximum standby current: 7µA
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Byte power-down feature
• Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII
package
, and OE features
Functional Description
[1]
The CY62137EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. Thi s
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 90% when addresses are not toggling.
The device can also be put into standby mode reducing power
consumption by more than 99% when deselected (CE
or both BLE
and BHE are HIGH). The input/output pins (I/O
HIGH
through I/O15) are placed in a high-impedance state when:
deselected (CE
HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE
BLE
HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE
Enable (BLE
I/O
(A
from I/O pins (I/O
specified on the address pins (A
) and Write Enable (WE) inputs LOW. If Byte Low
) is LOW, then data from I/O pins (I/O0 through
), is written into the location specified on the address pins
7
through A16). If Byte High Enable (BHE) is LOW, then data
0
through I/O15) is written into the location
8
through A16).
0
Reading from the device is accomplished by asserting Chip
Enable (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
to I/O7. If Byte High Enable (BHE) is
0
to I/O15. See
8
description of read and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
0
,
Power -Down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05443 Rev. *B Revised February 14, 2006
agram
A
DATA IN DRIVERS
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
CE
BHE
BLE
128K x 16
RAM Array
COLUMN DECODER
11
A
13
A12A
16
15
14
A
A
A
SENSE AMPS
I/O
– I/O
0
I/O8 – I/O
BHE
WE
CE
OE
BLE
7
15
[+] Feedback
CY62137EV30
MoBL
®
Pin Configurations
[2, 3]
VFBGA (Top View) 44 TSOP II (Top View)
A
A
A
NC
NC
A
A
A
4
3
0
3
5
14
12
9
5
6
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
I/O
I/O
I/O
I/O
WE
A
NC
2
I/O
I/O
1
Vcc
3
Vss
4
I/O
5
I/O
NC
11
A
B
0
C
2
D
E
F
6
G
7
H
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
A
A
A
A
A
A
A
A
A
CE
CC
SS
44
1
4
2
3
3
2
4
1
5
0
6
7
0
8
1
9
2
10
3
11
12
13
4
14
5
15
6
16
7
17
18
16
19
15
20
14
21
13
22
12
A
5
43
A
6
42
A
7
41
OE
40
BHE
39
BLE
38
I/O
15
37
I/O
14
36
I/O
13
35
I/O
12
34
V
SS
33
V
CC
32
I/O
11
I/O
31
10
30
I/O
9
29
I/O
8
NC
28
27
A
8
26
A
9
25
A
10
A
24
11
23
NC
1
BLE
I/O
I/O
V
SS
V
CC
I/O
I/O
NC
2
OE
BHE
8
I/O
10
9
I/O
11
I/O
12
I/O
13
14
NC
15
A
8
Product Portfolio
Product VCC Range (V)
Speed
(ns)
Operating ICC (mA)
f = 1MHz f = f
Min. Typ.
[7]
Max. Typ.
[7]
Max. Typ.
CY62137EV30-45LL 2.2V 3.0V 3.6V 45 ns 2 2.5 15 20 1 7
Note:
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the BGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Power Dissipation
max
[7]
Max. Typ.
Standby I
[7]
SB2
Max.
(µA)
Document #: 38-05443 Rev. *B Page 2 of 12
[+] Feedback
CY62137EV30
MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
DC Input Voltage
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
[4, 5]
........... –0.3V to 3.9V (V
Supply Voltage to Ground
Potential .............................–0.3V to 3.9V (V
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
...............–0.3V to 3.9V (V
CC(MAX)
CC MAX
+ 0.3V)
+ 0.3V)
Device Range
CY62137EV30-45LL Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics Over the Operating Range
Test Conditions 45 ns
Parameter Description
V
OH
V
OL
V
IH
Output HIGH Voltage IOH = –0.1 mA V
= –1.0 mA V
I
OH
Output LOW Voltage IOL = 0.1 mA V
= 2.1mA V
I
OL
Input HIGH Voltage V
= 2.2V to 2.7V 1.8 V
CC
VCC= 2.7V to 3.6V 2.2 V
V
I
I
I
I
IL
IX
OZ
CC
SB1
Input LOW Voltage V
Input Leakage Current GND < VI < V
Output Leakage
Current
VCC Operating Supply
Current
Automatic CE
Power-down Current
— CMOS
Inputs
I
SB2
Automatic CE
Power-down Current
— CMOS Inputs
Notes:
4. V
5. V
6. Full Device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after V
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
IH(max)=VCC
+0.75V for pulse durations less than 20ns.
= 2.2V to 2.7V –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
CC
GND < VO < VCC, Output Disabled –1 +1 µA
f = f
MAX
= 1/t
RC
f = 1 MHz 2.0 2.5
CE1 > VCC – 0.2V, CE2 < 0.2V
> V
V
IN
f = f
f = 0 (OE
CE
V
IN
f = 0, V
– 0.2V , V
CC
(Address and Data Only),
MAX
and WE), V
> VCC – 0.2V or CE2 < 0.2V,
1
> VCC – 0.2V or VIN < 0.2V,
= 3.60V
CC
= 2.20V 2.0 V
CC
= 2.70V 2.4 V
CC
= 2.20V 0.4 V
CC
= 2.70V 0.4 V
CC
–1 +1 µA
VCC = V
I
OUT
CMOS levels
IN
= 0 mA
< 0.2V)
= 3.60V
CC
CCmax
stabilization.
CC
CC MAX
Ambient
Temperature V
[7]
Max.
+ 0.3 V
CC
+ 0.3 V
CC
15 20 mA
17µA
17µA
CC
= V
CC(typ.)
, TA = 25°C.
+ 0.3V)
[6]
CC
UnitMin. Typ.
Document #: 38-05443 Rev. *B Page 3 of 12
[+] Feedback
CY62137EV30
MoBL
®
Capacitance (for all packages)
[8]
Parameter Description Test Conditions Max. Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
Parameter Description Test Conditions BGA TSOP II Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch, two-layer
[8]
printed circuit board
[8]
75 77 °C/W
10 13 °C/W
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
INCLUDING
30 pF
R2
VCC
GND
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
10%
JIG AND
SCOPE
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
R
TH
OUTPUT V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
V
DR
I
CCDR
[8]
t
CDR
[9]
t
R
Data Retention Waveform
V
CC
CE or
BHE
.BLE
Notes:
8. Tested initially and after any design or proc ess changes that may affect these parameters.
9. Full device operation requires linear V
VCC for Data Retention 1 V
Data Retention Current VCC= 1V
CE
> VCC – 0.2V ,
VIN > VCC – 0.2V or VIN < 0.2V
Chip Deselect to Data
0ns
Retention Time
Operation Recovery Time t
[10]
DATA RETENTION MODE
VDR> 1.5V
> 100 µs or stab le at V
CC(min.)
> 100 µs.
ramp from V
CC
V
CC(min)
t
CDR
DR
to V
CC(min.)
RC
V
[7]
Max. Unit
0.8 3 µA
CC(min)
t
R
ns
Document #: 38-05443 Rev. *B Page 4 of 12
[+] Feedback
CY62137EV30
MoBL
®
Switching Characteristics Over the Operating Range
[11]
45 ns
Parameter Description
UnitMin. Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
10.BHE
11.Test conditions for all parameters other th an tri-state p arameters assume signal transit ion time of 3 ns (1V/ns) or less, timi ng referen ce levels of V
pulse levels of 0 to V
12.At any given temperature and voltage condition, t
given device.
13.t
HZOE
14.The internal Write time of the memory is defined by the overlap of WE
of these signals can terminate a write by going INACTIVE. The dat a input set- up a nd h old timi ng sho uld be r eferenced t o the edge of the signal th at terminat es
the write.
[14]
.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
CC(typ.)
, t
, t
HZBE
, and t
HZCE
Read Cycle Time 45 ns
Address to Data Valid 45 ns
Data Hold from Address Change 10 ns
CE LOW to Data Valid 45 ns
OE LOW to Data Valid 22 ns
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[12]
[12, 13]
[12]
[12, 13]
5ns
18 ns
10 ns
18 ns
CE LOW to Power-Up 0 ns
CE HIGH to Power-Down 45 ns
BLE/BHE LOW to Data Valid 45 ns
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
[12]
[12, 13]
5ns
18 ns
Write Cycle Time 45 ns
CE LOW to Write End 35 ns
Address Set-Up to Write End 35 ns
Address Hold from Write End 0 ns
Address Set-Up to Write Start 0 ns
WE Pulse Width 35 ns
BLE/BHE LOW to Write End 35 ns
Data Set-Up to Write End 25 ns
Data Hold from Write End 0 ns
is less than t
HZCE
[12, 13]
[12]
18 ns
10 ns
, t
LZCE
is less than t
HZBE
, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
LZBE
, t
HZOE
is less than t
LZOE
, and t
is less than t
HZWE
WE LOW to High-Z
WE HIGH to Low-Z
, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
transitions are measured when the outputs enter a high- impedance state.
HZWE
CC(typ)
LZWE
/2, input
for any
Document #: 38-05443 Rev. *B Page 5 of 12
[+] Feedback
Switching Waveforms
t
OHA
[15, 16]
t
AA
t
RC
Read Cycle 1 (Address Transition Controlled)
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
CY62137EV30
MoBL
®
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
BHE/BLE
t
LZBE
DATA OUT
V
CC
SUPPLY
HIGH IMPEDANCE
t
LZCE
t
PU
CURRENT
[16, 17]
t
ACE
t
LZOE
t
DBE
t
DOE
50%
t
RC
t
PD
t
HZCE
t
HZOE
t
HZBE
HIGH
IMPEDANCE
DATA VALID
I
50%
CC
I
SB
Notes:
The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
15.
is HIGH for read cycle.
16.WE
17.Address valid prior to or coincident with CE
and BHE, BLE transition LOW.
Document #: 38-05443 Rev. *B Page 6 of 12
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 1 (WE
ADDRESS
CE
Controlled)
[14, 18, 19]
t
SCE
t
WC
CY62137EV30
MoBL
®
WE
BHE/BLE
OE
DATA I/O
NOTE
20
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
WE
t
SA
t
HZOE
[14, 18, 19]
t
AW
t
PWE
t
BW
t
SD
DATA
IN
t
WC
t
SCE
t
SA
t
AW
t
PWE
t
HA
t
HD
t
HA
t
BHE/BLE
BW
OE
DATA I/O
Notes:
18.Data I/O is high impedance if OE
19.If CE
goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state.
20.During this period, the I/Os are in output state and input signals should not be applied.
NOTE
20
= VIH.
t
HZOE
t
SD
DATA
IN
t
HD
Document #: 38-05443 Rev. *B Page 7 of 12
[+] Feedback
Switching Waveforms (continued)
Write Cycle No. 3 (WE
ADDRESS
CE
BHE/BLE
Controlled, OE LOW)
[19]
t
t
SCE
BW
t
WC
CY62137EV30
MoBL
®
t
SA
WE
DATAI/O
NOTE 20
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
ADDRESS
CE
BHE/BLE
t
SA
WE
t
HZWE
DATA I/O
NOTE 20
t
[19]
t
AW
AW
t
SCE
t
PWE
t
WC
t
PWE
t
BW
t
SD
DATAIN
t
SD
DATA
t
HA
t
HD
t
LZWE
t
HA
t
HD
IN
t
LZWE
Document #: 38-05443 Rev. *B Page 8 of 12
[+] Feedback
CY62137EV30
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-down St andby (I
X X X H H High Z Deselect/Power-down Standby (I
L H L L L Data Out (I/O
L H L H L Data Out (I/O
–I/O
I/O
8
L H L L H Data Out (I/O
I/O
–I/O7 in High Z
0
–I/O15) Read Active (ICC)
O
in High Z
15
–I/O7);
O
–I/O15);
8
Read Active (I
Read Active (I
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (I
L H H L H High Z Output Disabled Active (I
L L X L L Data In (I/O
L L X H L Data In (I/O
I/O
–I/O
8
L L X L H Data In (I/O8–I/O15);
–I/O7 in High Z
I/O
0
–I/O15) Write Active (ICC)
O
O
in High Z
15
–I/O7);
Write Active (I
Write Active (I
Ordering Information
Speed
(ns) Ordering Code
45 CY62137EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free) Industrial
45 CY62137EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
Package
Diagram Package T ype
MoBL
)
SB
)
SB
)
CC
)
CC
)
CC
)
CC
)
CC
)
CC
Operating
Range
®
Document #: 38-05443 Rev. *B Page 9 of 12
[+] Feedback
Package Diagrams
48-pin VFBGA (6 x 8 x 1 mm) (51-85150)
CY62137EV30
MoBL
®
0.25 C
8.00±0.10
A
0.55 MAX.
TOP VIEW
A1 CORNER
465231
A
B
C
D
E
F
G
H
A
B
6.00±0.10
0.21±0.05
0.10 C
0.75
5.25
8.00±0.10
2.625
B
0.15(4X)
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(48X)
65
1.875
0.75
6.00±0.10
3.75
A1 CORNER
1
234
A
B
C
D
E
F
G
H
51-85150-*D
SEATING PLANE
C
0.26 MAX.
1.00 MAX
Document #: 38-05443 Rev. *B Page 10 of 12
[+] Feedback
Package Diagrams (continued)
44-Pin TSOP II (51-85087)
CY62137EV30
MoBL
®
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semicond uctor. All product and company
names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05443 Rev. *B Pa ge 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch ange without notice. Cypress Semiconductor Corporation assumes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
Document History Page
Document Title: CY62137EV30 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 38-05443
REV. ECN NO. Issue Date
** 203720 See ECN AJU New Data Sheet
*A 234196 See ECN AJU Changed I
*B 427817 See ECN NXR Converted from Advanced Information to Final.
Orig. of
Change Description of Change
MAX at f=1MHz from 1.7 mA to 2.0 mA
Changed I
bin) to 15 mA and 12 mA respectively
CC
TYP from 12 mA (35 ns speed bin) and 10 mA (45 ns speed
CC
Changed ICC MAX from 20 mA (35 ns speed bin) and 15 mA (45 ns speed
bin) to 25 mA and 20 mA respectively
Changed I
Changed I
Changed I
Fixed typos on TSOP II pinout:
and I
SB1
SB1
CCDR
SB2
and I
SB2
from 1 µA to 2 µA
TYP from 0.6 µA to 0.7 µA
MAX from 1.5 µA to 2.5 µA
Pin 18-22: address lines
Pin 23: NC
Added Pb-free information
Removed 35 ns Speed Bin
Removed “L” version
Changed ball E3 from DNU to NC.
Removed the redundant footnote on DNU.
Moved Product Portfolio from Page # 3 to Page #2.
Changed I
1.5 mA to 2 mA at f=1 MHz
(Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
CC
Changed ICC (Typ) value from 12 mA to 15 mA at f = f
Changed I
2.5 µA to 7 µA.
SB1
and I
Typ. values from 0.7 µA to 1 µA and Max. values from
SB2
Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed V
Changed I
Added I
Corrected t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Changed t
Updated the Ordering Information table and replaced the Package Name
from 1.5V to 1V on Page# 4.
DR
from 2 µA to 3 µA.
CCDR
typical value.
CCDR
in Data Retention Characteristics from 100 µs to t
R
OHA , tLZCE
LZBE
LZOE
HZOE, tHZCE, tHZBE
SCE,tAW and tBW
PWE
from 20 ns to 25 ns
SD
and t
from 6 ns to 5 ns
from 3 ns to 5 ns
from 30 ns to 35 ns
column with Package Diagram.
from 6 ns to 10 ns
LZWE
and t
from 40 ns to 35 ns
HZWE
CY62137EV30
max
from 15 ns to 18 ns
=1/t
MoBL
RC
ns
RC
®
Document #: 38-05443 Rev. *B Page 12 of 12
[+] Feedback
Loading...