Cypress CY62137EV30 User Manual
Logic Block Di
CY62137EV30
MoBL
®
2-Mbit (128K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62137CV30
• Ultra-low standby power
— Typical standby current: 1
µA
— Maximum standby current: 7µA
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Byte power-down feature
• Offered in Pb-free 48-ball VFBGA and 44-pin TSOPII
package
, and OE features
Functional Description
[1]
The CY62137EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. Thi s
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 90% when addresses are not toggling.
The device can also be put into standby mode reducing power
consumption by more than 99% when deselected (CE
or both BLE
and BHE are HIGH). The input/output pins (I/O
HIGH
through I/O15) are placed in a high-impedance state when:
deselected (CE
HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE
BLE
HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE
Enable (BLE
I/O
(A
from I/O pins (I/O
specified on the address pins (A
) and Write Enable (WE) inputs LOW. If Byte Low
) is LOW, then data from I/O pins (I/O0 through
), is written into the location specified on the address pins
7
through A16). If Byte High Enable (BHE) is LOW, then data
0
through I/O15) is written into the location
8
through A16).
0
Reading from the device is accomplished by asserting Chip
Enable (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
to I/O7. If Byte High Enable (BHE) is
0
to I/O15. See
8
description of read and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
0
,
Power -Down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05443 Rev. *B Revised February 14, 2006
agram
A
DATA IN DRIVERS
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
CE
BHE
BLE
128K x 16
RAM Array
COLUMN DECODER
11
A
13
A12A
16
15
14
A
A
A
SENSE AMPS
I/O
– I/O
0
I/O8 – I/O
BHE
WE
CE
OE
BLE
7
15
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CY62137EV30
MoBL
®
Pin Configurations
[2, 3]
VFBGA (Top View) 44 TSOP II (Top View)
A
A
A
NC
NC
A
A
A
4
3
0
3
5
14
12
9
5
6
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
I/O
I/O
I/O
I/O
WE
A
NC
2
I/O
I/O
1
Vcc
3
Vss
4
I/O
5
I/O
NC
11
A
B
0
C
2
D
E
F
6
G
7
H
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
A
A
A
A
A
A
A
A
A
CE
CC
SS
44
1
4
2
3
3
2
4
1
5
0
6
7
0
8
1
9
2
10
3
11
12
13
4
14
5
15
6
16
7
17
18
16
19
15
20
14
21
13
22
12
A
5
43
A
6
42
A
7
41
OE
40
BHE
39
BLE
38
I/O
15
37
I/O
14
36
I/O
13
35
I/O
12
34
V
SS
33
V
CC
32
I/O
11
I/O
31
10
30
I/O
9
29
I/O
8
NC
28
27
A
8
26
A
9
25
A
10
A
24
11
23
NC
1
BLE
I/O
I/O
V
SS
V
CC
I/O
I/O
NC
2
OE
BHE
8
I/O
10
9
I/O
11
I/O
12
I/O
13
14
NC
15
A
8
Product Portfolio
Product VCC Range (V)
Speed
(ns)
Operating ICC (mA)
f = 1MHz f = f
Min. Typ.
[7]
Max. Typ.
[7]
Max. Typ.
CY62137EV30-45LL 2.2V 3.0V 3.6V 45 ns 2 2.5 15 20 1 7
Note:
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the BGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb, respectively.
Power Dissipation
max
[7]
Max. Typ.
Standby I
[7]
SB2
Max.
(µA)
Document #: 38-05443 Rev. *B Page 2 of 12
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CY62137EV30
MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
DC Input Voltage
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
[4, 5]
........... –0.3V to 3.9V (V
Supply Voltage to Ground
Potential .............................–0.3V to 3.9V (V
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
...............–0.3V to 3.9V (V
CC(MAX)
CC MAX
+ 0.3V)
+ 0.3V)
Device Range
CY62137EV30-45LL Industrial –40°C to +85°C 2.2V to 3.6V
Electrical Characteristics Over the Operating Range
Test Conditions 45 ns
Parameter Description
V
OH
V
OL
V
IH
Output HIGH Voltage IOH = –0.1 mA V
= –1.0 mA V
I
OH
Output LOW Voltage IOL = 0.1 mA V
= 2.1mA V
I
OL
Input HIGH Voltage V
= 2.2V to 2.7V 1.8 V
CC
VCC= 2.7V to 3.6V 2.2 V
V
I
I
I
I
IL
IX
OZ
CC
SB1
Input LOW Voltage V
Input Leakage Current GND < VI < V
Output Leakage
Current
VCC Operating Supply
Current
Automatic CE
Power-down Current
— CMOS
Inputs
I
SB2
Automatic CE
Power-down Current
— CMOS Inputs
Notes:
4. V
5. V
6. Full Device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after V
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
IH(max)=VCC
+0.75V for pulse durations less than 20ns.
= 2.2V to 2.7V –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
CC
GND < VO < VCC, Output Disabled –1 +1 µA
f = f
MAX
= 1/t
RC
f = 1 MHz 2.0 2.5
CE1 > VCC – 0.2V, CE2 < 0.2V
> V
V
IN
f = f
f = 0 (OE
CE
V
IN
f = 0, V
– 0.2V , V
CC
(Address and Data Only),
MAX
and WE), V
> VCC – 0.2V or CE2 < 0.2V,
1
> VCC – 0.2V or VIN < 0.2V,
= 3.60V
CC
= 2.20V 2.0 V
CC
= 2.70V 2.4 V
CC
= 2.20V 0.4 V
CC
= 2.70V 0.4 V
CC
–1 +1 µA
VCC = V
I
OUT
CMOS levels
IN
= 0 mA
< 0.2V)
= 3.60V
CC
CCmax
stabilization.
CC
CC MAX
Ambient
Temperature V
[7]
Max.
+ 0.3 V
CC
+ 0.3 V
CC
15 20 mA
17µA
17µA
CC
= V
CC(typ.)
, TA = 25°C.
+ 0.3V)
[6]
CC
UnitMin. Typ.
Document #: 38-05443 Rev. *B Page 3 of 12
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CY62137EV30
MoBL
®
Capacitance (for all packages)
[8]
Parameter Description Test Conditions Max. Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
Parameter Description Test Conditions BGA TSOP II Unit
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch, two-layer
[8]
printed circuit board
[8]
75 77 °C/W
10 13 °C/W
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
INCLUDING
30 pF
R2
VCC
GND
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
10%
JIG AND
SCOPE
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
R
TH
OUTPUT V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
V
DR
I
CCDR
[8]
t
CDR
[9]
t
R
Data Retention Waveform
V
CC
CE or
BHE
.BLE
Notes:
8. Tested initially and after any design or proc ess changes that may affect these parameters.
9. Full device operation requires linear V
VCC for Data Retention 1 V
Data Retention Current VCC= 1V
CE
> VCC – 0.2V ,
VIN > VCC – 0.2V or VIN < 0.2V
Chip Deselect to Data
0ns
Retention Time
Operation Recovery Time t
[10]
DATA RETENTION MODE
VDR> 1.5V
> 100 µs or stab le at V
CC(min.)
> 100 µs.
ramp from V
CC
V
CC(min)
t
CDR
DR
to V
CC(min.)
RC
V
[7]
Max. Unit
0.8 3 µA
CC(min)
t
R
ns
Document #: 38-05443 Rev. *B Page 4 of 12
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