• Ultra-low active power
—Typical active current: 1.5 mA @ f = 1 MHz
—Typical active current: 5.5 mA @ f = f
speed)
• Low and ultra-low standby power
• Easy memory expansion with CE
and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA
Functional Description
[1]
The CY62137CV25/30/33 and CY62137CV are high-performance CMOS static RAMs organized as 128K words by 16
bits. These devic es feature advanced circuit de sign to pro vide
ultra-low active current. This is ideal for providing More Battery
max
(70-ns
CY62137CV25/30/33 MoBL
CY62137CV MoBL
2M (128K x 16) Static RAM
Life™ (MoBL®) in portable applications such as cellular telephones. The devices also has an automatic power-down feature that significantly reduces power consumption by 80%
when addresses are not toggling. The device can also be put
into standby m ode reduci ng power con sumption by more tha n
99% when deselected (CE
HIGH). The input/output pins (I/O
in a high-impedance state when: deselected (CE
puts are dis abled (OE HIGH), both Byte High Enable and Byte
Low Enable a r e d is a bled ( B HE
operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW , then d ata f rom memory will a ppear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
HIGH or both BLE and BHE are
through I/O15) are plac ed
0
HIGH), out-
, BLE HIGH), or during a write
through A16).
0
to I/O7. If Byte High Enable (BHE) is
0
to I/O15. See
8
®
®
0
Logic Block Diagram
10
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Note:
1. For best practice recommendations, please refer to the Cypress applic a tion note “System Design Guidelines” on http://www.cypress.com.
DATA IN DRIVERS
ROW DECODER
COLUMN DECODER
11
A
Power- down
Circuit
128K x 16
RAM Array
2048 x 1024
14
A12A13A
– I/O
I/O
0
7
SENSE AMPS
15
16
A
A
CE
BHE
BLE
I/O8 – I/O
BHE
WE
CE
OE
BLE
15
Cypress Semiconductor Corporation•3901 North First Street•San Jose•CA 95134•408-943-2600
Document #: 38-05201 Rev. *D Revised September 20, 2002