Cypress CY62136VN User Manual

CY62136VN MoBL

®

2-Mbit (128K x 16) Static RAM

Features

• Temperature Ranges
— Industrial: –40°C to 85°C

— Automotive-A: –40°C to 85°C
— Automot ive-E: –40°C to 125°C

• High speed: 55 ns

• Wide voltage range: 2.7V–3.6V

• Ultra-low active, standby power

• Easy memory expansion with CE

and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Available in standard Pb-free 44-pin TSOP Type II,
Pb-free and non Pb-free 48-ball FBGA packages

Functional Description

[1]

The CY62136VN is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL

®

) in

Logic Block Diagram

A

10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

DATA IN DRIVERS

ROW DECODER

COLUMN DECODER

11

A

128K x 16

RAM Array

12

13

14

A

A

A

SENSE AMPS

15

16

A

A

portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE
I/O

) are placed in a high-impedance state when: deselected

15

HIGH), outputs are disabled (OE HIGH), BHE and BLE

(CE

HIGH). The input/output pins (I/O0 through

are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).

Writing to the device is accomplished by taking Chip Enable
(CE

) and Write Enable (WE) inputs LOW. If Byte Low Enable

) is LOW, then data from I/O pins (I/O0 through I/O7), is

(BLE
written into the location specified on the address pins (A
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A

through I/O15) is written into the location

8

through A16).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE

) and Output Enable (OE) LOW while forcing the

) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
the Truth Table at the back of this data sheet for a complete

to I/O15. See

8

description of read and write modes.

A

5

A

6

A

7

OE
BHE
BLE
I/O
I/O
I/O
I/O

V

SS

V

CC

I/O
I/O
I/O
I/O
NC
A

8

A

9

A

10

A

11

NC

[3]

15
14
13
12

11
10
9
8

I/O

– I/O

0

I/O8 – I/O

BHE
WE
CE
OE
BLE

Pin Configurations

TSOP II (Forward)

Top View

1

A

4

A

2

3

3

A

2

4

A

1

5

A

0

6

CE

7

15

I/O
I/O

I/O
I/O

V

V
I/O
I/O
I/O
I/O

WE
A
A

A
A

7

0

8

1

9

2

10

3

11

CC

12

SS

13

4

14

5

15

6

16

7

17
18

16

19

15

20

14

21

13

22

A

12

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

28
27
26
25
24

23

0

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06510 Rev. *A Revised August 3, 2006

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CY62136VN MoBL

Product Portfolio

Power Dissipation

VCC Range (V)

Product

Min Typ.

[2]

Max Typ.

Speed Ranges

CY62136VNLL 2.7 3.0 3.6 55 Industrial 7 20 1 15

Pin Configurations

55
70
70
70

[3]

Automotive-A 7 20 1 15

Industrial 7 15 1 15
Automotive-A 7 15 1 15
Automotive-E 7 20 1 20

FBGA

Top View

1

2

4

3

5

Operating, ICC (mA) Standby, I

[2]

Maximum Typ.

6

[2]

SB2

Maximum

®

(µA)

BLE

I/O

BHE

8

I/O

I/O

9

V

I/O

SS

V

I/O

CC

I/O

I/O

14

I/O

NC

15

NC

Notes:

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V

3. NC pins are not connected on the die.

0

A

3

A

5

10

NC

11

NC

12

A

14

13

A

12

A

A

9

8

A

OE

A

A

1

A

4

A

6

A

7

A

16

A

15

A

13

A

10

CE

I/O

I/O

I/O

I/O

WE

A

NC

2

I/O

I/O

1

V

CC

3

V

4

I/O

5

I/O

NC

11

SS

A

B

0

C

2

D

E

F

6

G

7

H

= VCC Typ, TA = 25°C.

CC

Document #: 001-06510 Rev. *A Page 2 of 12

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CY62136VN MoBL

®

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature..................................–65°C to +150°C

Ambient Temperature with

Output Current into Outputs (LOW)............................ 20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +4.6V

DC Voltage Applied to Outputs
in High-Z State

DC Input Voltage

[4]

....................................–0.5V to VCC + 0.5V

[4]

.................................–0.5V to VCC + 0.5V

Industrial −40°C to +85°C 2.7V to
Automotive-A –40°C to +85°C
Automotive-E –40°C to +125°C

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB1

I

SB2

Capacitance

C

IN

C

OUT

Notes:

4. V

IL

5. T

A

6. Tested initially and after any design or process ch anges that may affect these parameters.

Output HIGH Voltage VCC = 2.7V, IOH = −1.0 mA 2.4 2.4 V
Output LOW Voltage VCC = 2.7V, IOL = 2.1 mA 0.4 0.4 V
Input HIGH Volt age VCC = 3.6V 2.2 VCC +

Input LOW Voltage VCC = 2.7V –0.5 0.8 –0.5 0.8 V
Input Leakage

Current

GND < VI < V

CC

Ind’l –1 +1 –1 +1 µA
Auto-A –1 +1 –1 +1 µA
Auto-E –10 +10 µA

Output Leakage
Current

GND < VO < VCC,
Output Disabled

Ind’l –1 +1 –1 +1 µA
Auto-A –1 +1 –1 +1 µA
Auto-E –10 +10 µA

VCC Operating
Supply
Current

f = f
= 1/t

MAX

RC

VCC = 3.6V,
I

OUT

CMOS
Levels

= 0 mA,

Ind’l 7 20 7 15 mA
Auto-A 7 20 7 15
Auto-E 7 20

f = 1 MHz Ind’l 1 2 1 2 mA

Auto-A 1 2 1 2
Auto-E 1 2

Automatic CE
Power-down
Current—
CMOS Inputs

Automatic CE
Power-down
Current—
CMOS Inputs

[6]

CE > V

CC

> V

V

IN

CC

V

< 0.3V, f = f

IN

CE > V

CC

> V

V

IN

CC

V

< 0.3V, f = 0

IN

− 0.3V,

− 0.3V or

MAX

− 0.3V

− 0.3V or

Ind’l 100 100 µA
Auto-A 100 100 µA
Auto-E 100 µA
Ind’l 1 15 1 15 µA
Auto-A 1 15 1 15
Auto-E 1 20

Parameter Description Test Conditions Max. Unit

Input Capacitance TA = 25°C, f = 1 MHz,

V

Output Capacitance 8 pF

(min) = –2.0V for pulse durations less than 20 ns.

is the “Instant-On” case temperature.

CC

Range Ambient T emperature [TA]

-55 -70

[2]

Max. Min. Typ.

[2]

2.2 VCC +

0.5V

6pF

= V

CC(typ)

[5]

Max.

0.5V

V

CC

3.6V

UnitMin. Typ.

V

Document #: 001-06510 Rev. *A Page 3 of 12

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CY62136VN MoBL

®

Thermal Resistance

[6]

Parameter Description T e st Con ditions TSOPII FBGA Unit

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Still Air , soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board

60 55 °C/W

22 16 °C/W

AC Test Loads and Waveforms

V

CC

OUTPUT

INCLUDING

R1

V

CC

OUTPUT

30 pF

JIG AND

SCOPE

R2

INCLUDING

JIG AND

(a)

Parameters Value Unit

R1 1105 Ohms
R2 1550 Ohms

R

TH

V

TH

5 pF

SCOPE

R1

(b)

R2

VCC Typ

GND

Equivalent to: THÉ VENIN EQUIVALENT

10%

Rise Time:
1 V/ns

OUTPUT V

ALL INPUT PULSES

90%

645 Ohms

1.75 Volts

90%

Fall Time:
1 V/ns

(c)

RTH

10%

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions

V

DR

I

CCDR

VCC for Data Retention 1.0 V
Data Retention Current VCC = 1.0V, CE > VCC − 0.3V,

VIN > VCC − 0.3V or VIN < 0.3V ,

t

CDR

t

R

[6]

[7]

Chip Deselect to Data
Retention Time

Operation Recovery Time 70 ns

Data Retention Waveform

DATA RETENTION MODE

V

V

CC

CE

Note:

7. Full device operation requires linear V

8. No input may exceed V

CC

+ 0.3V

ramp from V

CC

CC(min.)

t

CDR

DR

to V

100 ms or stable at V

CC(min) >

VDR> 1.0 V

[9]

CC(min) >

100 ms.

Min. Typ.

[2]

Max. Unit

0.5 7.5 µA

0ns

V

CC(min.)

t

R

Document #: 001-06510 Rev. *A Page 4 of 12

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CY62136VN MoBL

®

Switching Characteristics Over the Operating Range

[9]

55 ns 70 ns

Parameter Description

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

t

DBE

t

LZBE

t

HZBE

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

BW

t

SD

t

HD

t

HZWE

t

LZWE

Notes:

9. Test conditions assume signal transition time of 5 n s or less, timing reference levels of 1.5V, input pulse levels of 0 to V
I

OL/IOH

10.At any given temperature and voltage condition, t

11. t

HZOE

12.The internal write time of the memory is defined by the overlap of CE
terminate a write by going HIGH. The data input set-up and hold timing should be refe renced to the rising edge of the signal that terminates the write.

13.The minimum write cycle time for write cycle 3 (WE

[12, 13]

and 30-pF load capacitance.

, t

, and t

HZCE

Read Cycle Time 55 70 ns
Address to Data Valid 55 70 ns
Data Hold from Address Change 10 10 ns
CE LOW to Data Valid 55 70 ns
OE LOW to Data Valid 25 35 ns
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z

[10]

[10, 11]

[10]

[10, 11]

55ns

25 25 ns

10 10 ns

25 25 ns
CE LOW to Power-up 0 0 ns
CE HIGH to Power-down 55 70 ns
BLE / BHE LOW to Data Valid 25 35 ns
BLE / BHE LOW to Low-Z
BLE / BHE HIGH to High-Z

[10, 11]

[12]

55ns

25 25 ns

Write Cycle Time 55 70 ns
CE LOW to Write End 45 60 ns
Address Set-up to Write End 45 60 ns
Address Hold from Write End 0 0 ns
Address Set-up to Write Start 0 0 ns
WE Pulse Width 40 50 ns
BLE / BHE LOW to Write End 50 60 ns
Data Set-up to Write End 25 30 ns
Data Hold from Write End 0 0 ns
WE LOW to High-Z
WE HIGH to Low-Z

are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

HZWE

[10, 11]
[10]

is less than t

HZCE

controlled, OE LOW) is the sum of t

, t

LZCE

HZOE

LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can

20 25 ns

510ns

typ., and output loading of the specified

CC

is less than t

HZWE

, and t

LZOE

and tSD.

HZWE

is less than t

for any given device.

LZWE

UnitMin. Max. Min. Max.

Document #: 001-06510 Rev. *A Page 5 of 12

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Switching Waveforms

Read Cycle No. 1

[14, 15]

ADDRESS

DATA OUT PREVIOUS DATA VALID

t

OHA

CY62136VN MoBL

t

RC

t

AA

DATA VALID

®

Read Cycle No. 2

[15, 16]

CE

OE

BHE/BLE

t

LZBE

DATA OUT

V

CC

SUPPLY

HIGH IMPEDANCE

t

LZCE

t

PU

CURRENT

Notes:

14.Device is continuously selected. OE
is HIGH for read cycle.

15.WE

16.Address valid prior to or coincident with CE

, CE = VIL.

t

ACE

t

DOE

t

LZOE

t

DBE

50%

transition LOW.

t

RC

t

PD

t

HZCE

t

HZOE

t

HZBE

HIGH

IMPEDANCE

DATA VALID

I

50%

CC

I

SB

Document #: 001-06510 Rev. *A Page 6 of 12

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Switching Waveforms (continued)

Write Cycle No. 1 (WE Controlled)

ADDRESS

CE

[12, 17, 18]

t

WC

CY62136VN MoBL

®

WE

BHE/BLE

OE

DATA I/O

NOTE

19

Write Cycle No. 2 (CE Controlled)

ADDRESS

CE

BHE/BLE

t

SA

t

HZOE

[12, 17, 18]

t

AW

t

BW

t

PWE

t

SD

t

HA

t

HD

DATAINVALID

t

WC

t

SCE

t

SA

t

AW

t

BW

t

HA

t

WE

DATA I/O

Notes:

17.Data I/O is high impedance if OE

goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

18.If CE

19.During this period, the I/Os are in output state and input signals should not be applied.

= VIH.

PWE

t

SD

DATAINVALID

t

HD

Document #: 001-06510 Rev. *A Page 7 of 12

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Switching Waveforms (continued)

Write Cycle No. 3 (WE Controlled, OE LOW)

ADDRESS

CE

[13, 18]

t

WC

CY62136VN MoBL

®

BHE/BLE

t

WE

DATA I/O

SA

NOTE 19

t

HZWE

Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)

ADDRESS

CE

BHE/BLE

t

SA

WE

t

AW

[19]

t

AW

t

WC

t

BW

t

BW

t

SD

DATAINVALID

t

HA

t

t

t

LZWE

HA

HD

DATA I/O

NOTE 19

t

HZWE

t

SD

DATAINVALID

t

LZWE

t

HD

Document #: 001-06510 Rev. *A Page 8 of 12

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Typical DC and AC Characteristics

CY62136VN MoBL

®

Normalized Operating Current

1.4

1.2

1.0

0.8

CC

I

0.6

0.4

0.2

0.0

1.7 2.2 2.7 3.2 3.7

80
70

60
50
40

AA (ns)

30

T

20
10

1.0

vs. Supply Voltage

SUPPLY VOLTAGE (V)

Access Time vs. Supply Voltage

1.9

2.7

2.8

MoBL

MoBL

3.7

Standby Current vs. Supply Voltage

35
30

25
20

SB (µA)

15

I

10
5

0

1.0

1.9

SUPPLY VOLTAGE (V)

2.7

2.8

MoBL

3.7

SUPPLY VOLTAGE (V)

Truth Table

CE WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X High-Z Deselect/Power-down Standby (ISB)

L H L L L Data Out (I/O0–I/O15) Read Active (ICC)
L H L H L Data Out (I/O0–I/O7);

I/O

–I/O

8

in High-Z

15

L H L L H Data Out (I/O8–I/O15);

I/O

–I/O7 in High-Z

0

Read Active (ICC)

Read Active (ICC)

L H L H H High-Z Deselect/Output Disabled Active (ICC)
L H H L L High-Z Deselect/Output Disabled Active (ICC)
L H H H L High-Z Deselect/Output Disabled Active (ICC)
L H H L H High-Z Deselect/Output Disabled Active (ICC)
L L X L L Data In (I/O0–I/O15) Write Active (ICC)
L L X H L Data In (I/O0–I/O7);

–I/O

I/O

8

in High-Z

15

L L X L H Data In (I/O8–I/O15);

I/O

–I/O7 in High-Z

0

Write Active (ICC)

Write Active (ICC)

Document #: 001-06510 Rev. *A Page 9 of 12

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CY62136VN MoBL

Ordering Information

Speed

(ns) Ordering Code

55 CY62136VNLL-55ZXI 51-85087 44-pin TSOP II (Pb-Free) Industrial

CY62136VNLL-55BAI 51-85096 48-Ball (7.00 mm x 7.00 mm) FBGA
CY62136VNLL-55ZSXA 51-85087 44-pin TSOP II (Pb-Free) Automotive-A

70 CY62136VNLL-70ZXI 51-85087 44-pin TSOP II (Pb-Free) Industrial

CY62136VNLL-70BAI 51-85096 48-Ball (7.00 mm x 7.00 mm) FBGA
CY62136VNLL-70BAXA 51-85096 48-Ball (7.00 mm x 7.00 mm) FBGA (Pb-Free) Automotive-A
CY62136VNLL-70ZSXA 51-85087 44-pin TSOP II (Pb-Free)
CY62136VNLL-70ZSXE 51-85087 44-pin TSOP II (Pb-Free) Automotive-E

Please contact your local Cypress sales representative for availability of these parts

Package Diagrams

Package

Diagram Package Type

44-pin TSOP II (51-85087)

®

Operating

Range

51-85087-*A

Document #: 001-06510 Rev. *A Page 10 of 12

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Package Diagrams (continued)

48-Ball (7.00 mm x 7.00 mm) FBGA (51-85096)

CY62136VN MoBL

®

7.00±0.10

A

0.25 C

B

0.53±0.05

0.36

PIN 1 CORNER
(LASER MARK)

A

B

C

D

E

F

G

H

SEATING PLANE

C

TOP VIEW

7.00±0.10

BOTTOM VIEW

Ø0.05 M C

Ø0.25 M C A B

6512 3 4

0.75

5.25

7.00±0.10

2.625

A

B

0.15(4X)

0.21±0.05

1.20 MAX.

0.10 C

Ø0.30±0.05(48X)

564321

1.875

0.75

3.75

7.00±0.10

51-85096-*F

PIN 1 CORNER

A

B

C

D

E

F

G

H

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semicond uctor Corporatio n. All prod uct a nd
company names mentioned in this document are th e products of their respective holders.

Document #: 001-06510 Rev. *A Page 11 of 12

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch ange without notice. Cypress Semiconductor Corporation assumes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furtherm ore, Cypress do es not authori ze its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title: CY62136VN MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 001-06510

REV. ECN NO. Issue Date

** 426503 See ECN RXU New Data Sheet

*A 488954 See ECN NXR Added Automotive product

Orig. of
Change Description of Change

Updated ordering Information table

CY62136VN MoBL

®

Document #: 001-06510 Rev. *A Page 12 of 12

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