— Automotive-A: –40°C to 85°C
— Automot ive-E: –40°C to 125°C
• High speed: 55 ns
• Wide voltage range: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE
and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in standard Pb-free 44-pin TSOP Type II,
Pb-free and non Pb-free 48-ball FBGA packages
Functional Description
[1]
The CY62136VN is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DATA IN DRIVERS
ROW DECODER
COLUMN DECODER
11
A
128K x 16
RAM Array
12
13
14
A
A
A
SENSE AMPS
15
16
A
A
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE
I/O
) are placed in a high-impedance state when: deselected
15
HIGH), outputs are disabled (OE HIGH), BHE and BLE
(CE
HIGH). The input/output pins (I/O0 through
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
) is LOW, then data from I/O pins (I/O0 through I/O7), is
(BLE
written into the location specified on the address pins (A
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A
through I/O15) is written into the location
8
through A16).
0
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
the Truth Table at the back of this data sheet for a complete
to I/O15. See
8
description of read and write modes.
A
5
A
6
A
7
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
SS
V
CC
I/O
I/O
I/O
I/O
NC
A
8
A
9
A
10
A
11
NC
[3]
15
14
13
12
11
10
9
8
I/O
– I/O
0
I/O8 – I/O
BHE
WE
CE
OE
BLE
Pin Configurations
TSOP II (Forward)
Top View
1
A
4
A
2
3
3
A
2
4
A
1
5
A
0
6
CE
7
15
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
A
A
A
7
0
8
1
9
2
10
3
11
CC
12
SS
13
4
14
5
15
6
16
7
17
18
16
19
15
20
14
21
13
22
A
12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
0
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Document #: 001-06510 Rev. *A Revised August 3, 2006