Cypress CY62136EV30 User Manual
CY62136EV30
MoBL
®
2-Mbit (128K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62136CV30
• Ultra low standby power
— Typical standby current: 1µA
— Maximum standby current: 7µA
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
, and OE features
Functional Description
[1]
The CY62136EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE
) are placed in a high-impedance state when: deselected
I/O
15
(CE
HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE
or during a write operation (CE
HIGH). The input/output pins (I/O0 through
, BLE HIGH),
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
(BLE
) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A
through I/O15) is written into the location
8
through A16).
0
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
to I/O7. If Byte High Enable (BHE) is
0
to I/O15. See
8
description of read and write modes.
0
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05569 Rev. *B Revised January 6, 2006
DATA IN DRIVERS
ROW DECODER
COLUMN DECODER
11
A
128K x 16
RAM Array
13
A12A
–I/O
I/O
0
7
SENSE AMPS
16
15
14
A
A
A
I/O8–I/O
15
BHE
WE
CE
OE
BLE
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CY62136EV30
MoBL
®
Pin Configuration
1
2
OE
BLE
I/O
BHE
8
I/O
I/O
V
V
I/O
I/O
NC
SS
CC
10
9
I/O
11
I/O
12
I/O
13
14
NC
15
A
8
Product Portfolio
[2, 3]
VFBGA (Top View) 44 TSOP II (Top View)
4
3
A
A
A
NC
NC
A
14
A
12
A
[4]
0
3
5
9
5
6
A
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
CE
I/O
I/O
I/O
I/O
WE
A
NC
2
I/O
I/O
1
Vcc
3
Vss
4
I/O
5
I/O
NC
11
A
B
0
C
2
D
E
F
6
G
7
H
CE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
A
A
A
A
A
A
A
A
A
CC
SS
44
1
4
2
3
3
2
4
1
5
0
6
7
0
8
1
9
2
10
3
11
12
13
4
14
5
15
6
16
7
17
18
16
19
15
20
14
21
13
22
12
A
5
43
A
6
42
A
7
41
OE
40
BHE
39
BLE
38
I/O
37
I/O
36
I/O
35
I/O
34
V
SS
33
V
CC
32
I/O
31
I/O
30
I/O
29
I/O
NC
28
27
A
8
26
A
9
25
A
10
A
24
11
23
NC
15
14
13
12
11
10
9
8
Power Dissipation
Operating ICC (mA)
[4]
Max. Typ.
max
[4]
Max. Typ.
Standby I
[4]
SB2
Max.
Product VCC Range (V)
Min. Typ.
[4]
Speed
(ns)
Max. Typ.
CY62136EV30LL 2.2 3.0 3.6 45 2 2.5 15 20 1 7
Notes:
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, and H6 in the BGA package are address expansion pins for 4 Mbit, 8 Mbit, 16 Mbit and 32 Mbit, respectively.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, TA = 25°C.
(µA)f = 1MHz f = f
Document #: 38-05569 Rev. *B Page 2 of 12
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CY62136EV30
MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential ..............................–0.3V to 3.9V (V
DC Voltage Applied to Outputs
in High-Z State
[5,6]
................–0.3V to 3.9V (V
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
OH
OL
IH
IL
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Volt age V
Input LOW Voltage V
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-down
Current — CMOS
Inputs
I
SB2
Automatic CE
Power-down
Current — CMOS
Inputs
Capacitance (for all packages)
IOH = –0.1 mA V
= –1.0 mA V
I
OH
IOL = 0.1 mA V
= 2.1mA V
I
OL
= 2.2V to 2.7V 1.8 V
CC
= 2.7V to 3.6V 2.2 V
V
CC
= 2.2V to 2.7V –0.3 0.6 V
CC
= 2.7V to 3.6V –0.3 0.8 V
V
CC
GND < VI < V
GND < VO < VCC, Output Disabled –1 +1 µA
f = f
= 1/tRCVCC = V
MAX
f = 1 MHz 2 2.5
CE > VCC−0.2V ,
V
f = f
f = 0 (OE
V
–0.2V, VIN<0.2V)
IN>VCC
(Address and Data Only),
MAX
, and WE),
= 3.60V
CC
CE > VCC – 0.2V,
V
> VCC – 0.2V or VIN < 0.2V, f = 0,
IN
V
= 3.60V
CC
[8]
CC MAX
CC MAX
CC
+ 0.3V)
+ 0.3V)
[5, 6, 7]
= 2.20V 2.0 V
CC
= 2.70V 2.4 V
CC
= 2.20V 0.4 V
CC
= 2.70V 0.4 V
CC
CMOS levels
CCmax, IOUT
DC Input Voltage
[5,6]
............ –0.3V to 3.9V (V
CC MAX
+ 0.3V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Device Range
[7]
Ambient
T emperature V
CC
[7]
CY62136EV30LL Industrial –40°C to +85°C 2.2V - 3.6V
45 ns
[4]
Max.
+ 0.3 V
CC
+ 0.3 V
CC
UnitMin. Typ.
–1 +1 µA
= 0 mA
15 20 mA
17µA
17µA
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
5. V
6. V
7. Full Device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after V
8. Tested initially and after any design or process ch anges that may affect these parameters.
= –2.0V for pulse durations less than 20 ns.
IL(min.)
IH(max)=VCC
+0.75V for pulse durations less than 20ns.
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
CC(typ)
stabilization.
CC
10 pF
Document #: 38-05569 Rev. *B Page 3 of 12
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CY62136EV30
MoBL
®
Thermal Resistance
[8]
VFBGA
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
[8]
[8]
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
Package
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
INCLUDING
JIG AND
30 pF
R2
VCC
GND
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
10%
SCOPE
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.
V
DR
I
CCDR
[8]
t
CDR
[9]
t
R
Data Retention Waveform
V
CC
CE
VCC for Data Retention 1.0 V
Data Retention Current VCC= 1.0V
CE
> VCC – 0.2V,
V
> VCC – 0.2V or VIN < 0.2V
IN
Chip Deselect to Data
Retention Time
Operation Recovery
Time
V
CC(min)
t
CDR
DATA RETENTION MODE
ALL INPUT PULSES
90%
OUTPUT V
[8, 9]
90%
10%
R
TH
0ns
t
RC
VDR> 1.0 V
V
TSOP II
Package Unit
75 77 °C/W
10 13 °C/W
Fall Time = 1 V/ns
TH
[4]
Max. Unit
0.8 3 µA
CC(min)
t
R
ns
Notes:
9. Full device operation requires linear V
ramp from V
CC
DR
to V
> 100 µs or stab le at V
CC(min.)
CC(min.)
> 100 µs.
Document #: 38-05569 Rev. *B Page 4 of 12
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