CYPRESS CY62128V User Manual
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CY62128V Family
128K x 8 Static RAM
Features
• Low volt age rang e :
—2.7V–3.6V (CY62128V)
—2.3V–2.7V (CY62128V25)
—1.6V–2.0V (CY62128V18)
• Low active power and standby power
• Easy memory expansion wit h CE
and OE fe atures
• TTL-compatible inputs and outputs
• Aut om atic power-d ow n when deselected
• CMOS for optimum speed/power
Functional Description
The CY62128V f ami ly i s com posed of three hi gh-per formanc e
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enabl e ( CE
), an active HIGH Chip Enable (CE2), an active
1
Logic Block Diagram
I/O
I/O1
I/O
I/O
I/O
I/O
I/O
I/O
62128V-1
CE
CE
WE
OE
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
ROW DECODER
A
7
A
8
1
2
512x256x 8
ARRAY
COLUMN
DECODER
11
10
9
A
A
A
SENSE AMPS
POWER
DOWN
14
15
12
16
A
A
A
A13A
LOW Output Enable (OE
) and three-state drivers. These devices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE
Enable two (CE
) and Write Enable (WE) inputs LOW and the Chip
1
) input HIGH. Data on the eig ht I/O pins (I/O
2
through I/O7) is then written into the location specified on the
address pins (A
through A16).
0
Reading from the device is accomplished by taking Chip Enable one (CE
Write Enable (WE
) and Output Enable (OE) LOW whil e forcing
1
) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
through I/O7) are placed in a
0
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write oper ation ( CE
0
2
3
4
5
6
7
LOW , CE2 HIGH, and W E LOW) .
1
Pin
Configurations
Top View
SOIC
NC
A
A
A
I/O
I/O
I/O
GND
1
16
2
3
14
4
12
5
A
7
A
6
6
A
5
7
A
8
4
A
9
3
A
10
2
A
1
11
A
12
0
0
13
1
14
2
15
16
V
32
CC
31
A
15
30
CE
2
29
WE
28
A
13
27
A
8
26
A
9
25
A
11
24
OE
23
A
10
22
CE
1
I/O
21
7
I/O
6
20
I/O
5
19
I/O
4
18
17
I/O
62128V-2
3
0
1
A
4
16
A
5
15
A
14
6
A
13
7
A
12
12
V
CE
A
A
NC
A
WE
A
A
11
14
10
16
9
CC
8
7
15
2
6
5
13
4
A
8
3
A
9
2
1
11
TSOP I
Reverse Pinout
Top View
(not to scale)
Cypress Semiconductor Corporation
A
CE
V
A
WE
A
NC
A
A
A
1
11
2
A
9
3
A
8
4
13
5
6
2
7
15
8
CC
9
10
16
11
14
12
12
A
13
7
A
14
6
15
A
5
16
A
4
TSOP I / STSOP
Top View
(not to scale)
A
17
3
A
18
2
A
19
1
A
20
0
I/O
21
0
I/O
22
1
I/O
23
2
GND
24
I/O
3
25
I/O
4
26
I/O
5
27
I/O
6
28
I/O
7
29
CE
1
30
A
10
31
OE
32
62128V-3
32
OE
31
A
10
30
CE
1
29
I/O
7
28
I/O
6
27
I/O
5
26
I/O
4
25
I/O
3
24
GND
23
I/O
2
I/O
22
1
I/O
21
0
20
A
0
A
19
1
18
A
2
A
17
3
62128V-4
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 27, 2000
CY62128V Family
Maximum Ratings
(Abov e which the useful life may be impair ed. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current............. .......... .. .......... .. .......... .. ... >200 mA
Operating Range
Power Applied.............................................–55°C to +1 2 5 °C
Supply Voltage to Ground Potential
(Pin 28 to Pi n 14 ) ........ ... ............ ............ ........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
[1]
....................................–0.5V to VCC + 0.5V
[1]
.................................–0.5V to VCC + 0.5V
Range Ambient Tem perature V
Commercial 0°C to +70°C 1.6V to 3.6V
Industrial –40°C to +85°C 1.6V to 3.6V
CC
Product Portfolio
Po wer Dissipation (Commercial)
VCC Range
Product Min. Typ.
[2]
Max. Speed Typ.
CY62128V 2.7V 3.0V 3.6V 55, 70 ns 20 mA 40 mA 0.4 µA 100 µA (XL = 10 µA)
CY62128V25 2.3V 2.5V 2.7V 100 ns 15 mA 20 mA 0.3 µA 50 µA (LL = 12 µA)
CY62128V18 1.6V 1.8V 2.0V 200 ns 10 mA 15 mA 0.3 µA 30 µA (LL = 10 µA)
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min. Typ.
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Notes:
1. V
IL
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Output HIGH Volt age VCC = Min., IOH = –1.0 mA 2.4 V
Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
Input HIG H Voltage 2 V
Input LOW Voltage –0.5 0.8 V
Input Load Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 ±1 +1
VCC Operating Suppl y
Current
Auto matic CE
Power-Down Current—
TTL Inpu ts
(min.) = –2.0V for pulse durations of less than 20 ns.
VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
= 1/t
RC
Max. VCC, CE > VIH,
V
> VIH or
IN
V
< VIL, f = f
IN
MAX
Operating (ICC) Standby (I
[2]
Maximum Typ.
[2]
Maximum
CY62128V-55/70
[2]
Max. Unit
CC
+0.5V
–1 ±1 +1
Com’l,
70 ns
Ind’l,
L 20 40 mA
LL, XL 20 40
LL 23 50
55 ns
Ind’l,
70 ns
Com’l,
70 ns
Coml,
L 20 40
LL 20 40
L 15 300
LL, XL 15 300
LL 17 350
55 ns
Ind’l L 15 300
LL 15 300
= VCC Typ., TA = 25°C.
CC
SB2
)
V
µA
µA
µA
2
CY62128V Family
Electrical Characteristics
Over the Operating Range
CY62128V-55/70
Parameter Description Test Conditions Min. Typ.
I
SB2
Auto matic CE
Power-Down Current—
CMOS Inputs
Max. VCC,
CE
> VCC – 0.3V
V
> VCC – 0.3V
IN
or V
< 0.3V, f = 0
IN
Com’l L 0.4 100
LL 15
XL 10
Ind’l L 100
LL 30
Electrical Characteristics
Over the Operating Range
CY62128V25-100 CY62128V18-200
Parameter Description Test Conditions Min. Typ.
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Volt age VCC = Min., IOH = –0.1 mA 2.4 0.8*
Output LOW Voltage VCC = Min., IOL = 0.1 mA 0.4 0.2 V
Input HIG H Voltage 2 V
Input LOW Voltage –0.5 0.8 –0.5 0.3*
Input Load Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output
–1 ±1 +1 –1 ±0.1 +1
–1 ±1 +1 –1 ±0.1 +1
Disabled
VCC Operating Suppl y
Current
Auto matic CE
Power-Down Current—
TTL Inpu ts
Auto matic CE
Power-Down Current—
CMOS Inputs
VCC = Max.,
I
= 0 mA,
OUT
f = f
MAX
= 1/t
RC
Max. VCC, CE > VIH,
V
> VIH or
IN
V
< VIL, f = f
IN
MAX
Max. VCC,
CE
> VCC – 0.3V
V
> VCC – 0.3V
IN
or V
< 0.3V, f = 0
IN
L 15 20 10 15 mA
LL
L 15 300 5 100
LL
L 0.4 50 0.4 30
LL 12 10
[2]
Max. Min. Typ.
CC
+0.5
V
0.7*
V
Indust’l Temp Range LL 24 20
Capacitance
[3]
CC
CC
[2]
Max. Unit
µA
µA
µA
µA
µA
[2]
Max. Unit
V
CC
+0.3
V
CC
V
V
V
µA
µA
µA
µA
µA
µA
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.0V
Output Capacitance 8 pF
CC
6 pF
3
AC Test Loads and Waveforms
CY62128V Family
V
CC
OUTPUT
INCLUDING
JIG AND
Equivalent to: THÉ VENIN EQUIVALENT
R1
50 pF
SCOPE
OUTPUT V
R2
62128V–5
R
TH
1.8V
GND
<5ns
10%
ALL INPUT PULSES
90%
90%
10%
<5ns
62128V–6
Parameters 3.3V 2.5V 1.8V Unit
R1 1213 15909 10800 Ohms
R2 1378 4487 4154 Ohms
R
TH
V
TH
Data Rete n ti o n C h ar acteristics
Parameter Description Conditions
V
DR
I
CCDR
t
CDR
t
R
[3]
VCC for Da ta Rete ntion 1.6 V
Data Retention Current Com ’l L VCC = 2V
Chip Deselect to Data Retention Time 0 ns
Operation Recov ery Time t
645 3500 3000 Ohms
1.75V 0.55V 0.50V Volts
(Over the Operating Range)
[4]
Min. Typ.
[2]
0.4 10
CE
LL,
XL
Ind’l L 20
LL 20
> VCC – 0.3V,
V
> VCC – 0.3V or
IN
V
< 0.3V
IN
No input may exceed
V
+0.3V
CC
RC
Max. Unit
µA
10
µA
µA
µA
ns
Data Retention Waveform
V
CC
CE
Note:
4. No input may exceed V
CC
+0.3V.
t
CDR
DATA RETENTION MODE
VDR> 1.6 V
4
1.8V1.8V
t
R
C62128V–7
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