Cypress CY62128EV30 User Manual
CY62128EV30
MoBL® 1 Mbit (128K x 8) Static RAM
Features
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
12
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A15A
16
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A
10
A
11
CE
1
CE
2
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
■ Very high speed: 45 ns
❐ Temperature ranges:
• Industrial: –40°C to +85°C
• Automotive-A: –40°C to +85°C
• Automotive-E: –40°C to +125°C
■ Wide voltage range: 2.20V – 3.60V
■ Pin compatible with CY62128DV30
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 4 μA
■ Ultra low active power
❐ Typical active current: 1.3 mA @ f = 1 MHz
■ Easy memory expansion with CE
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin
STSOP packages
, CE2 and OE features
1
Functional Description
The CY62128EV30
module organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE
input and output pins (IO
impedance state when the device is deselected (CE
CE
LOW), the outputs are disabled (OE HIGH), or a write
2
operation is in progress (CE
LOW).
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO
pins is then written into the location specified on the Address pin
(A0 through A16).
To read from the device, take Chip Enable (CE1 LOW and CE
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE
) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the IO pins.
[1]
is a high performance CMOS static RAM
®
) in portable
HIGH or CE2 LOW). The eight
1
through IO7) are placed in a high
0
LOW and CE2 HIGH and WE
1
1
HIGH or
1
LOW and CE
2
2
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05579 Rev. *D Revised March 28, 2008
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CY62128EV30
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
STSOP
Top View
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
9
10
32
1
2
3
4
5
6
7
8
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
26
25
26
27
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
15
17
18
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
IO
7
IO
6
IO
5
IO
4
A
2
NC
IO
0
IO
1
IO
2
CE
1
OE
A
10
IO
3
A
1
A
0
A
11
CE
2
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
Pin Configuration
[2]
Table 1. Product Portfolio
Product Range VCC Range (V)
Min Typ
[3]
Max T yp
Speed
(ns)
CY62128EV30LL Ind’l/Auto-A 2.2 3.0 3.6 45 1.3 2.0 11 16 1 4
CY62128EV30LL Auto-E 2.2 3.0 3.6 55 1.3 4.0 11 35 1 30
Document #: 38-05579 Rev. *D Page 2 of 11
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = f
[3]
Max Typ
[3]
max
Max Typ
Standby I
[3]
SB2
(µA)
Max
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CY62128EV30
Maximum Ratings
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max)
= VCC+0.75V for pulse durations le ss th an 20 ns.
6. Full device AC operation assumes a 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
7. Only chip enables (CE
1
and CE2) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature.................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground
Potential..........................................–0.3V to V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
[4, 5]
.........................–0.3V to V
[4,5]
.......................–0.3V to V
CC(max)
CC(max)
CC(max)
+ 0.3V
+ 0.3V
+ 0.3V
Electrical Characteristics
(Over the Operating Range)
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Device Range
CY62128EV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to
Auto-E –40°C to +125°C
Ambient
Temperature
V
CC
3.6V
[6]
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
Output HIGH Voltage IOH = –0.1 mA 2.0 2.0 V
IOH = –1.0 mA, V
CC
> 2.70V
Output LOW Voltage IOL = 0.1 mA 0.4 0.4 V
Input HIGH Voltage V
Input LOW Voltage V
IOL = 2.1 mA, V
= 2.2V to 2.7V 1.8 V
CC
V
= 2.7V to 3.6V 2.2 V
CC
= 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V
CC
> 2.70V 0.4 0.4 V
CC
VCC= 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
[7]
Input Leakage Current GND < VI < V
CC
Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –4 +4 μA
VCC Operating Supply
Current
Automatic CE
Power down
Current — CMOS Inputs
Automatic CE
Power down
Current — CMOS Inputs
f = f
= 1/t
max
RCVCC
f = 1 MHz 1.3 2.0 1.3 4.0 mA
CE
> VCC−0.2V, CE2 < 0.2V
1
V
> VCC–0.2V, V
IN
f = f
f = 0 (OE
(Address and Data Only),
max
and WE), V
= V
I
= 0 mA
OUT
CMOS levels
< 0.2V)
IN
CC
CE1 > VCC – 0.2V, CE2 < 0.2V
V
> VCC – 0.2V or VIN < 0.2V,
IN
f = 0, V
= 3.60V
CC
CCmax
= 3.60V
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Typ
[3]
Max Min Typ
[3]
Max
2.4 2.4 V
+
CC
0.3V
CC
0.3V
1.8 V
+
2.2 V
CC
0.3V
CC
0.3V
+
+
–1 +1 –4 +4 μA
11 16 11 35 mA
14 135μA
14 130μA
Unit
V
V
Document #: 38-05579 Rev. *D Page 3 of 11
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CY62128EV30
Capacitance
Note
8. Teste d initially and after any design or process changes that may affect these parameters.
9. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalentto: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
(For all packages)
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
[8]
Input Capacitance TA = 25°C, f = 1 MHz,
V
= V
CC
Output Capacitance 10 pF
CC(typ)
10 pF
Thermal Resistance
Parameter Description Test Conditions TSOP I SOIC STSOP Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
Figure 1. AC Test Loads and Waveforms
33.01 48.67 32.56 °C/W
3.42 25.86 3.59 °C/W
Parameters 2.50V 3.0V Unit
R1 16667 1103 Ω
R2 15385 1554 Ω
R
TH
V
TH
8000 645 Ω
1.20 1.75 V
Data Retention Characteristics
(Over the Operating Range)
Parameter Description Conditions Min Typ
V
DR
I
CCDR
t
CDR
[9]
t
R
[7]
[8]
VCC for Data Retention 1.5 V
Data Retention Current VCC = 1.5V,
CE
> VCC − 0.2V or CE2 < 0.2V,
1
V
> VCC − 0.2V or VIN < 0.2V
IN
Ind’l/Auto-A 3 μA
Auto-E 30 μA
Chip Deselect to Data Retention
Time
Operation Recovery Time t
[3]
Max Unit
0ns
RC
ns
Document #: 38-05579 Rev. *D Page 4 of 11
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