Cypress CY62128E User Manual
MoBL® CY62128E
1-Mbit (128K x 8) Static RAM
Features
A
0
IO
0
IO
7
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
12
SENSE AMPS
POWER
DOWN
WE
OE
A
13
A
14
A15A
16
ROW DECODER
COLUMN DECODER
128K x 8
ARRAY
INPUT BUFFER
A
10
A
11
CE
1
CE
2
Logic Block Diagram
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Voltage range: 4.5V to 5.5V
■ Pin compatible with CY62128B
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 4 μA (Industrial)
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin TSOP I packages
, CE2, and OE features
1
Functional Description
The CY62128E
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE
eight input and output pins (IO
impedance state when the device is deselected (CE
CE
LOW), the outputs are disabled (OE HIGH), or a write
2
operation is in progress (CE
To write to the device, take Chip Enable (CE1 LOW and CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO
pins (IO
on the address pins (A
0
To read from the device, take Chip Enable (CE
HIGH) and Output Enable (OE) LOW while forcing Write Enable
) HIGH. Under these conditions, the contents of the memory
(WE
location specified by the address pins appear on the IO pins.
[1]
is a high performance CMOS static RAM
®
) in portable
HIGH or CE2 LOW). The
1
through IO7) are placed in a high
0
LOW and CE2 HIGH and WE LOW)
1
HIGH or
1
through IO7) is then written into the location specified
through A16).
0
LOW and CE
1
2
2
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05485 Rev. *F Revised August 4, 2008
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MoBL® CY62128E
Pin Configuration
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
STSOP
Top Vi ew
(not to scale)
30
28
29
31
24
19
23
22
21
20
18
13
17
16
15
14
11
12
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
9
10
32
1
2
3
4
5
6
7
8
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
26
25
26
27
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
IO
2
IO
1
GND
IO
7
IO
4
IO
5
IO
6
IO
0
CE
1
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
IO
3
A
1
A
0
A
3
A
2
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
32-Pin SOIC
Top View
NC
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
V
SS
V
CC
CE
2
WE
OE
CE
1
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, TA = 25°C.
4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (t
AA
, t
ACE
) and 25 ns (t
DOE
) are guaranteed.
[2]
Product Portfolio
Speed
(ns)
[4]
f = 1MHz f = f
[3]
1.3 2 11 16 1 4
Product Range VCC Range (V)
Min Typ
[3]
Max Typ
CY62128ELL Ind’l/Auto-A 4.5 5.0 5.5 45
CY62128ELL Auto-E 4.5 5.0 5.5 55 1.3 4 11 35 1 30
Document #: 38-05485 Rev. *F Page 2 of 12
Power Dissipation
Operating ICC (mA)
Max Typ
[3]
max
Max Typ
Standby I
[3]
SB2
(µA)
Max
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MoBL® CY62128E
Maximum Ratings
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 μs ramp time from 0 to V
CC
(min) and 200 μs wait time after V
CC
stabilization.
8. Only chip enables (CE
1
and CE2) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground
Potential...............................–0.5V to 6.0V (V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
[5, 6]
.............. –0.5V to 6.0V (V
[5, 6]
........... –0.5V to 6.0V (V
CC(max)
CC(max)
CC(max)
+ 0.5V)
+ 0.5V)
+ 0.5V)
Electrical Characteristics (Over the Operating Range)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Device Range
Ambient
Temperature
CY62128ELL Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V
Auto-E –40°C to +125°C
[7]
V
CC
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB2
OH
OL
IH
IL
[8]
Output HIGH
Vol tage
Output LOW
Vol tage
Input HIGH Voltage V
Input LOW voltage V
Input Leakage
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power down
Current—CMOS
Inputs
Capacitance (For all Packages)
IOH = –1 mA 2.4 2.4 V
IOL = 2.1 mA 0.4 0.4 V
= 4.5V to 5.5V 2.2 V
CC
= 4.5V to 5.5V –0.5 0.8 –0.5 0.8 V
CC
GND < VI < V
CC
GND < VO < VCC, Output Disabled –1 +1 –4 +4 μA
f = f
= 1/tRCVCC = V
max
f = 1 MHz 1.3 2 1.3 4
I
= 0 mA
OUT
CMOS levels
CE1 > VCC – 0.2V or CE2 < 0.2V,
> VCC – 0.2V or VIN < 0.2V,
V
IN
f = 0, V
[9]
CC
= V
CC(max)
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF
CC(max)
V
= V
CC
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Typ
[3]
Max Min Typ
+ 0.5 2.2 V
CC
[3]
Max
+ 0.5 V
CC
–1 +1 –4 +4 μA
11 16 11 35 mA
14 130μA
10 pF
CC(typ)
Unit
Document #: 38-05485 Rev. *F Page 3 of 12
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MoBL® CY62128E
Thermal Resistance
3.0V
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
CC(min)
V
CC(min)
t
CDR
VDR> 2.0V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
10. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
11. CE
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Notes
10. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 μs or stable at V
CC(min)
> 100 μs.
11. CE
is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
[9]
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveform
Parameters Val ue Unit
R1 1800 Ω
R2 990 Ω
R
TH
V
TH
1.77 V
SOIC
Package
STSOP
Package
48.67 32.56 33.01 °C/W
25.86 3.59 3.42 °C/W
639 Ω
TSOP
Package
Unit
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Ty p
V
DR
I
CCDR
[9]
t
CDR
[10]
t
R
Data Retention Waveform
Document #: 38-05485 Rev. *F Page 4 of 12
VCC for Data Retention 2 V
[8]
Data Retention Current VCC= VDR, CE1 > VCC − 0.2V or CE2 < 0.2V,
> VCC - 0.2V or VIN < 0.2V
V
IN
Ind’l/Auto-A 4 μA
Auto-E 30 μA
Chip Deselect to Data
Retention Time
Operation Recovery
Time
[11]
[3]
Max Unit
0ns
t
RC
ns
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