—Industrial: –40°C to 85°C
—Automotive: –40°C to 125°C
• 4.5V–5.5V operation
• CMOS for optimum speed/power
• Low active power
(70 ns, LL version, Commercial, Industrial)
—82.5 mW (max.) (15 mA)
• Low standby power
(70 ns, LL version, Commercial, Industrial)
—110 µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
, CE2, and OE options
1
Functional Description
[1]
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1),
an active HIGH Chip Enable (CE
Enable (OE
), and three-state drivers. This device has an
), an active LOW Output
2
automatic power-down feature that reduces power
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
Enable Tw o (CE
through I/O7) is then written into the location specified on the
address pins (A
) and Write Enable (WE) inputs LOW and Chip
1
) input HIGH. Data on the eight I/O pins (I/O
2
through A16).
0
Reading from the device is accomplished by taking Chip
Enable One (CE
Write Enable (WE
) and Output Enable (OE) LOW while forcing
1
) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
through I/O7) are placed in a
0
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
LOW, CE2 HIGH, and WE LOW).
1
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
0
1
Logic Block Diagram
I/O
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CE
1
CE
2
WE
OE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
512x256x8
ROW DECODER
ARRAY
COLUMN
DECODER
10
9
A
A
SENSE AMPS
POWER
DOWN
11
14
15
16
12
A
A
A
A
A13A
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
Cypress Semiconductor Corporation•3901 North First Street•San Jose, CA 95134•408-943-2600
Document #: 38-05300 Rev. *C Revised March 7, 2005
2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an averag e of the distribution across normal production
variations as measured at V
-I/O7. Data lines. Used as input or output lines depending on operation
0
. Write Enable, Active LOW. When selected LOW , a WRITE is conducted. When selected HIGH, a READ
is conducted.
. Chip Enable 1, Active LOW.
1
. Chip Enable 2, Active HIGH.
2
. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
. Power supply for the device
CC
= 5.0V, TA = 25°C, and t
CC
AA
= 70 ns.
1
7
6
5
4
3
2
1
0
Document #: 38-05300 Rev. *CPage 2 of 11
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CY62128B
MoBL
®
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Current into Outputs (LOW).........................................20 mA
T est conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA / JESD51.
66.1797.44105.1497.44°C/W
30.8726.0514.0926.05°C/W
ParameterDescriptionTest ConditionsMax.Unit
C
IN
C
OUT
Input CapacitanceTA = 25°C, f = 1 MHz,
V
= 5.0V
Output Capacitance9pF
CC
9pF
AC Test Loads and Waveforms
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:THÉVENIN EQUIVALENT
OUTPUT
R1 1800
(a)
Ω
639Ω
R2
990
OUTPUT
Ω
1.77V
5V
5 pF
INCLUDING
JIG AND
SCOPE
R1 1800Ω
(b)
R2
990Ω
V
CC
GND
Rise TIme:
1 V/ns
ALL INPUT PULSES
90%
10%
90%
10%
Fall TIme
1 V/ns
Data Retention Waveform
DATA RETENTION MODE
2 V
VDR
>
CE
V
CC
1
VCC, min.
t
CDR
or
CE
2
Data Retention Characteristics
(Over the Operating Range for “LL” version only)
ParameterDescriptionConditionsMin.Typ.Max.Unit
V
DR
I
CCDR
t
CDR
t
R
Note:
6. Tested initially and after any design or process changes that may affect t hese parameters.
VCC for Data Retention2.0V
Data Retention CurrentV
= V
CC
or CE
0.3V
= 2.0V, CE1 ≥ VCC – 0.3V,
DR
≤ 0.3V, VIN ≥ VCC – 0.3V or, VIN ≤
2
Chip Deselect to Data Retention
Time
Operation Recovery Time70ns
VCC, min.
t
R
1.515µA
0ns
Document #: 38-05300 Rev. *CPage 4 of 11
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CY62128B
MoBL
®
Switching Characteristics
[7]
Over the Operating Range
ParameterDescription
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time5570ns
Address to Data Valid5570ns
Data Hold from Address Change55ns
CE1 LOW to Data Valid, CE2 HIGH to Data Valid5570ns
OE LOW to Data Valid2035ns
OE LOW to Low Z00ns
OE HIGH to High Z
[7, 9]
CE1 LOW to Low Z, CE2 HIGH to Low Z
CE1 HIGH to High Z, CE2 LOW to High Z
CE1 LOW to Power-up, CE2 HIGH to Power-up00ns
CE1 HIGH to Power-down, CE2 LOW to Power-down5570ns
[10]
Write Cycle Time5570ns
CE1 LOW to Write End, CE2 HIGH to Write End4560ns
Address Set-up to Write End4560ns
Address Hold from Write End00ns
Address Set-up to Write Start00ns
WE Pulse Width4550ns
Data Set-up to Write End2530ns
Data Hold from Write End00ns
WE HIGH to Low Z
WE LOW to High Z
[9]
[8, 9]
[9]
[8, 9]
62128B-5562128B-70
UnitMin.Max.Min.Max.
2025ns
55ns
2025ns
55ns
2025ns
Switching Waveforms
, and t
[12, 13]
t
RC
t
t
OHA
PREVIOUS DATA VALIDDATA VALID
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV fr om steady -state vo ltag e.
HZWE
CC
+ 0.5V.
, CE1 = VIL, CE2 = VIH.
HZCE
AA
is less than t
, t
LZCE
is less than t
HZOE
LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
1
LZOE
, and t
HZWE
is less than t
for any given device.
LZWE
Read Cycle No.1
ADDRESS
DATA OUT
Notes:
7. T est conditi ons assume signal transi tion time of 5 ns or less, t iming refer ence levels of 1.5V, input pulse le vels of 0 to 3.0V, and output loadin g of the specified
8. t
9. At any given temperature and voltage condition, t
10. The internal write time of the memory is defined by the overlap of CE
11. No input may exceed V
12. Device is continuously selected. OE
13. WE
and 100-pF load capacitan ce.
I
OL/IOH
, t
HZOE
HZCE
and the transition of any of these sign als can terminat e the write. The in put data set -up and hold timi ng should be refe renced to the leading edge of the signal that terminates
the write.
is HIGH for read cycle.
Document #: 38-05300 Rev. *CPage 5 of 11
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Switching Waveforms (continued)
PU
t
LZCE
[13, 14]
t
ACE
t
LZOE
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
1
CE
2
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
t
DOE
50%
t
RC
t
HZOE
t
HZCE
DATA VALID
CY62128B
IMPEDANCE
t
PD
MoBL
HIGH
®
I
CC
50%
I
SB
Write Cycle No. 1 (CE1 or CE2 Controlled)
ADDRESS
CE
1
t
CE
2
WE
DATA I/O
Notes:
14. Address valid prior to or coincident with CE
15. Data I/O is high impedance if OE
16. If CE
goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
1
= VIH.
SA
transition LOW and CE2 transition HIGH.
1
[15, 16]
t
AW
t
WC
t
SCE
t
t
PWE
t
SD
SCE
t
HA
t
HD
DATA VALID
Document #: 38-05300 Rev. *CPage 6 of 11
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Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
AW
t
SA
WE
OE
[15, 16]
t
WC
t
PWE
CY62128B
MoBL
t
HA
®
DATA I/O
NOTE
17
t
HZOE
Write Cycle No.3 (WE Controlled, OE LOW)
ADDRESS
CE
1
CE
2
t
SA
WE
DATAI/O
NOTE 17
t
HZWE
[15, 16]
t
AW
t
t
SCE
SCE
t
WC
t
PWE
t
SD
DATAINVALID
t
SD
DATA VALID
t
HA
t
LZWE
t
HD
t
HD
Note:
17. During this period the I/Os are in the output state and input sig nals should not be applied.
Document #: 38-05300 Rev. *CPage 7 of 11
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Truth Table
CY62128B
MoBL
®
CE
HXXXHigh ZPower-downStandby (ISB)
XLXXHigh ZPower-downStandby (I
CE
1
LHLHData OutReadActive (I
LHXLData InWriteActive (ICC)
LHHHHigh ZSelected, Outputs Disabled Active (ICC)
OEWEI/O0–I/O
2
7
ModePower
)
SB
)
CC
Ordering Information
Speed (ns)Ordering CodePackage NamePackage TypeOperating Range
CY62128BLL-55SXIS3432-Lead 450-Mil SOIC (Pb-Free)Industrial
CY62128BLL-55SCS3432-Lead 450-Mil SOICCommercial
CY62128BLL-55SXCS3432-Lead 450-Mil SOIC (Pb-Free)Commercial
CY62128BLL-55ZIZ3232-Lead TSOP Type IIndustrial
CY62128BLL-55ZXIZ3232-Lead TSOP Type I (Pb-Free)Industrial
CY62128BLL-55ZAIZA3232-Lead STSOP Type IIndustrial
CY62128BLL-55ZAXIZA3232-Lead STSOP Type I (Pb-Free)Industrial
CY62128BLL-55ZRIZR3232-Lead Reverse TSOP Type IIndustrial
CY62128BLL-70SXIS3432-Lead 450-Mil SOIC I (Pb-Free)Industrial
CY62128BLL-70SCS3432-Lead 450-Mil SOIC ICommercial
CY62128BLL-70SXCS3432-Lead 450-Mil SOIC I (Pb-Free)Commercial
CY62128BLL-70SES3432-Lead 45 0-Mil SOIC IAutomotive
CY62128BLL-70SXES3432-Lead 450-Mil SOIC I (Pb-Free)Automotive
CY62128BLL-70ZIZ3232-Lead TSOP Type IIndustrial
CY62128BLL-70ZCZ3232-Lead TSOP Type ICommercial
CY62128BLL-70ZEZ3232-Lead TSOP Type IAutomotive
CY62128BLL-70ZXEZ3232-Lead TSOP Type I (Pb-Free)Automotive
CY62128BLL-70ZAIZA3232-Lead STSOP Type IIndustrial
CY62128BLL-70ZAXIZA3232-Lead STSOP Type I (Pb-Free)Industrial
CY62128BLL-70ZAEZA3232-Lead STSOP Type IAutomotive
CY62128BLL-70ZAXEZA3232-Lead STSOP Type I (Pb-Free)Automotive
CY62128BLL-70ZRXEZR3232-Lead Reverse TSOP Type I (Pb-Free)Automotive
Document #: 38-05300 Rev. *CPage 8 of 11
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Package Diagrams
1732
32-Lead (450 MIL) Molded SOIC S34
116
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
CY62128B
MoBL
®
0.101[2.565]
0.111[2.819]
0.050[1.270]
BSC.
0.793[20.142]
0.817[20.751]
0.014[0.355]
0.020[0.508]
0.004[0.102]
SEATING PLANE
MIN.
0.118[2.997]
MAX.
0.004[0.102]
0.006[0.152]
0.012[0.304]
32-Lead Thin Small Outline Package Type I (8x20 mm) Z32
0.023[0.584]
0.039[0.990]
0.047[1.193]
0.063[1.600]
51-85081-*B
51-85056-*D
Document #: 38-05300 Rev. *CPage 9 of 11
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Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package (8x13.4 mm) ZA32
CY62128B
MoBL
®
32-Lead Reverse Thin Small Outline Package ZR32
51-85094-*D
51-85089-*C
All product and company names mentioned in this document are the trademarks of their respective holders.
Document Title: CY62128B MoBL® 1-Mbit (128K x 8) St atic RAM
Document Number: 38-05300
REV.ECN NO.
**11656606/20/02D SGC hanged from Spec number: 38-00524 to 38-05300
*A12660106/09/03JUIChanged CE to CE
*B23913 4See ECNAJUAdded Thermal Resistance table
*C334398See ECNSYTAd ded Pb-Free part numbers to the Ordering info on Page #8
Issue
Date
Orig. of
ChangeDescription of Change
and added CE2 ≤ 0.3V in Data Retention Characteristics table
Removed these part numbers from Ordering Information table:
CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC,
CY62128BLL-70ZAC, CY62128BLL-70ZRI, CY62128BLL-70ZRC
Added Automotive product information
1
CY62128B
MoBL
®
Document #: 38-05300 Rev. *CPage 11 of 11
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