AN55427
Cypress Powerline Communication Board Design Analysis
Associated Part Family: CY8CPLC10, CY8CPLC20
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visit http://www.cypress.com/go/AN55427.
This application note describes the on-board circuitry of Cypress’s high voltage 110 V to 240 V AC Powerline
Communication (PLC) boards (CY3274). It describes the filter, coupling circuit, and power supply design. It also explains
the selection of critical components necessary to meet performance and compliance requirements.
Contents
1 Introduction .................................................................. 1
2 High Voltage Board Design ......................................... 2
2.1 Transmit Signal Path ........................................... 5
2.2 Receive Signal Path ............................................ 6
2.3 Signal Path Component Requirements ............... 6
2.4 Power Supply ...................................................... 7
2.5 Power Path Component Requirements ............... 9
2.6 PLC Device Interface ........................................ 10
3 Low Voltage Board Design ........................................ 12
1 Introduction
Powerlines are widely available communication media for PLC technology all over the world. The pervasiveness of
powerline also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable
quality of powerlines around the world, implementing robust communication over powerline has been an engineering
challenge for years. The Cypress PLC solution enables secure and reliable communication over powerline. The
features of Cypress PLC include:
Integrated Powerline PHY modem with optimized filters and amplifiers to work with lossy high voltage and low
voltage powerlines.
Powerline optimized network protocol that supports bidirectional communication with acknowledgement based
signaling. In case of data packet loss due to louder noise on the powerline, the transmitter has the capability to
retransmit the data.
The powerline network protocol supports 8-bit CRC for error detection and data packet retransmission.
A Carrier Sense Multiple Access (CSMA) scheme is built into the network protocol; it minimizes collision between
packet transmissions on the powerline, supports multiple masters, and enables reliable communication on a
bigger network.
A block diagram of the PLC solution with the CY8CPLC20 programmable PLC chip is shown in Figure 1. To interface
the device to the powerline, a coupling circuit is required.
3.1 Transmit Signal Path......................................... 13
3.2 Receive Signal Path.......................................... 13
3.3 Signal Path Component Requirements ............. 14
3.4 Power Supply .................................................... 14
3.5 PLC Device Interface ........................................ 15
4 Summary ................................................................... 17
Document History ............................................................ 18
Worldwide Sales and Design Support ............................. 19
www.cypress.com Document No. 001-55427 Rev. *E 1
Cypress Powerline Communication Board Design Analysis
Figure 1. Cypress PLC Solution Block Diagram
Cypress provides the CY3274 High Voltage Programmable PLC Development Kit (DVK) for evaluating the Cypress
PLC solution.
The CY3274 is designed with the filtering and power supply circuitry to operate on 110-240 V AC powerlines. They
are compliant to the following CENELEC and FCC standards:
Powerline Signaling (EN50065-1:2001, FCC Part 15)
Powerline Immunity (EN50065-2-1:2003,
EN61000-3-2/3)
Safety (EN60950)
The CY3274 kits are used to develop a powerline controller and embedded host application on the CY8CPLC20
Programmable PLC device. They contain many user interface options such as I2C, RS232, GPIO, analog voltage,
LCD display, and LED to develop a full application.
The following sections describe the design of the filter circuits and power supplies, including the selection of critical
components for meeting performance and compliance requirements.
2 High Voltage Board Design
This section describes the design of the high voltage (110 V AC to 240 V AC) PLC boardCY3274.
The design includes all circuitry to meet the requirements for signaling on high voltage lines according to the
EN50065-1:2001 standard. The high voltage boards include an isolated offline switch mode power supply accepting
input voltages in the range of 110-240 V AC, and 50-60 Hz line frequency, operating off the same powerlines that
carry the communication signaling.
The design contains transmit signal filtering and amplification to meet the conducted emissions requirements of the
CENELEC and FCC standards. It also has receive signal filtering and signal isolation external to the Cypress PLC
device. This provides a compact and low cost implementation that is adaptable to a wide variety of PLC applications.
The schematic in Figure 2 shows the Cypress high voltage board’s transmit filter and amplification, receive filter, and
coupling circuit to the high voltage powerline. The Bill of Materials (BOM) of these components is listed in Table 1.
www.cypress.com Document No. 001-55427 Rev. *E 2
Cypress Powerline Communication Board Design Analysis
Figure 2. Cypress High Voltage PLC Board Signal Filtering, Amplification, and Coupling Circuit
www.cypress.com Document No. 001-55427 Rev. *E 3
Cypress Powerline Communication Board Design Analysis
Description
Designator
Qty.
Value
Manufacturer
Manufacturer Part#
Vendor
VPN
High Voltage Coupling Circuit
Capacitor Metal Poly
Film 0.15uF 300VAC
X1
C9 1 0.15 µF
Panasonic
ECQ-U3A154MG
Digikey
P11117-ND
Isolation
Transformer
T1 1
Precision Components, Inc.
0505-0821G
http://www.pcitransformers.com
Transient Voltage
Suppressor 400W
12V BIDIRECT SMA
D10 1
Micro Commercial Co
SMAJ12CA-TP
Digikey
SMAJ12CA-TPMSCT-ND
Transmitter Circuit
Transmit Amplification
Capacitor Ceramic
1.0uF 16V X7R 0603
C12, C13,
C14, C15
4
1.0 µF
Taiyo Yuden
EMK107B7105KA-T
Digikey
587-1241-1-ND
Capacitor Ceramic
0.10uF 10% 16V
X7R 0603
C18, C24
2
0.1 µF
Panasonic
ECJ-1VB1C104K
Digikey
PCC1762CT-ND
Capacitor Ceramic
10.0uF 10% 25V
X5R 1206
C19 1 10.0 µF
Taiyo Yuden
TMK316BJ106KL-T
Digikey
587-1337-1-ND
Capacitor Ceramic
0.01uF 25V X7R
0603
C36 1 0.01 µF
AVX
06033C103JAT2A
Digikey
06033C103JAT2A-ND
Transistor NPN HV
40V 1A SOT-89
Q1 1
Zetex
FCX491ATA
Digikey
FCX491ACT-ND
Transistor PNP HV
40V 1A SOT-89
Q2 1
Zetex
FCX591ATA
Digikey
FCX591ACT-ND
Transistor NPN
SOT-23
Q3 1
Fairchild
MMBT3904LT1
Digikey
MMBT3904LT1INCT-ND
Resistor 22.1 1%
1/10W 0603
R14 1 22.1
Yageo
RC0603FR-0722R1L
Digikey
311-22.1HRCT-ND
Resistor 10.0k 1%
1/10W 0603
R15, R17,
R18, R28,
R29, R30,
R31
7
10.0 k
Yageo
RC0603FR-0710KL
Digikey
311-10.0KHRTR-ND
Resistor 4.02k 1%
1/10W 0603
R16 1 4.02 k
Yageo
RC0603FR-074K02L
Digikey
311-4.02KHRCT-ND
Resistor 4.99 1%
1/10W 0603
R23 1 4.99
Yageo
RC0603FR-074R99L
Digikey
311-4.99HRCT-ND
Resistor 1.00k 1%
1/10W 0603
R25 1 1.00 k
Yageo
RC0603FR-071KL
Digikey
311-1.00KHRTR-ND
Op-Amp 190MHz
U4 1
National Semiconductor
LMH6639MF/NOPB
Digikey
LMH6639MFCT-ND
Transmit Filtering for FCC/CENELEC
Capacitor Ceramic
0.10uF 10% 16V
X7R 0603
C16, C17
2
0.1 µF
Panasonic
ECJ-1VB1C104K
Digikey
PCC1762CT-ND
Capacitor Ceramic
1000PF 1% 5V NP0
0603
C20, C21,
C22, C23
4
1.0 nF, 1%
AVX
06033A102FAT2A
Digikey
06033A102FAT2A-ND
Resistor 37.4k 1%
1/10W 0603
R19, R20
2
37.4 k
Yageo
RC0603FR-0737K4L
Digikey
311-37.4KHRCT-ND
Resistor 3.83k 1%
1/10W 0603
R21 1 3.83 k
Yageo
RC0603FR-073K83L
Digikey
311-3.83KHRCT-ND
Resistor 7.50k 1%
1/10W 0603
R22 1 7.50 k
Yageo
RC0603FR-077K5L
Digikey
311-7.50KHRTR-ND
Resistor 36.5 1%
1/10W 0603
R26 1 36.5
Yageo
RC0603FR-0736R5L
Digikey
311-36.5HRCT-ND
Resistor 41.2 1%
1/10W 0603
R27 1 41.2
Yageo
RC0603FR-0741R2L
Digikey
311-41.2HRCT-ND
Op-Amp 190MHz
U2, U3 2
National Semiconductor
LMH6639MF/NOPB
Digikey
LMH6639MFCT-ND
Receiver Circuit
Capacitor Ceramic
0.01uF 25V X7R
0603
C10 2 0.01 µF
AVX
06033C103JAT2A
Digikey
06033C103JAT2A-ND
Capacitor Ceramic
1500pF 10% 50V
X7R 0603
C41 1 1500 pF
Yageo
CC0603KRX7R9BB152
Digikey
311-1184-2-ND
Dual Schottky Diode
D6 1
ST Micro
BAT54SFILM
Digikey
497-2522-1-ND
Inductor 1mH 10%
1007
L5 1 1 mH
Taiyo Yuden
CB2518T102K
Digikey
587-2195-1-ND
Resistor 2.0k 1%
1/10W 0603
R10 1 2.0 k
Yageo
RC0603FR-072KL
Digikey
311-2.00KHRCT-ND
Resistor 20.0k 1%
1/10W 0603
R9, R11 2 20.0 k
Yageo
RC0603FR-0720KL
Digikey
311-20.0KHRCT-ND
Table 1. Cypress High Voltage PLC Board Signal Filtering, Amplification, and Coupling BOM
www.cypress.com Document No. 001-55427 Rev. *E 4
2.1 Transmit Signal Path
2.1.1 Transmit Filter
The FSK transmit signal TX is generated on the FSK_OUT pin of the Cypress PLC device as a low amplitude
(~125 mVp-p), unfiltered signal. This signal is applied to the input of an external transmit filter block consisting of
opamps U2 and U3, and their related passive components. The transmit filter is a fourth order Chebyshev response
band pass filter, designed for 1.5 dB maximum pass band ripple. It provides 16.5 dB of gain at the center frequency
of 133 kHz, suppression of -20 dBc at the 150 kHz band limit, and -50 dBc and -60 dBc at the second and third
carrier harmonics, respectively. The transmit filter response is shown graphically in Figure 3.
Figure 3. Cypress High Voltage PLC Board Transmit Filter Response
Cypress Powerline Communication Board Design Analysis
The power supply for the transmit filter opamps is a filtered version of the VPWR supply. This prevents the relatively
large currents produced by the power amplifier from feeding back into the high-Q filter circuit through the power
supply and causing oscillations. Hence, it is advisable to avoid routing the high current transmit signal near the filter
circuit.
2.1.2 Transmit Amplification
The filtered transmit data signal is applied to the power amplifier, which consists of opamp U4, transistors Q1 and Q2,
and associated passive components. The power amplifier provides an additional 12 dB voltage gain, and is capable
of driving low impedance loads presented by the powerline.
2.1.3 High Voltage Coupling
The transmit signal from the power amplifier is driven on to the powerlines via the isolation transformer T1. Capacitor
C14 provides DC isolation for the transmitter on the device side, and C9 provides line frequency isolation on the line
side.
When the device is not actively transmitting, the signal TX_DISABLE is asserted from the PLC device. This disables
the external power amplification circuitry to save power and make the transmit amplification circuit have a high
impedance so that the receive signal is not attenuated. Note that the transmit filter stage amplifiers U2 and U3 are
always enabled, so that there is no spurious noise output on the line due to filter ringing at startup.
www.cypress.com Document No. 001-55427 Rev. *E 5
2.2 Receive Signal Path
The receive signal is coupled from the line into the kit via the same isolation transformer, T1, as is used by the
transmitter.
2.2.1 Receive Filter
Capacitor C10 provides DC isolation. Resistor R10 provides a signal input impedance for the receiver. This resistor,
in combination with D6, provides signal limiting to protect the receiver circuitry from high amplitude transmitter signals
and any large signals coupled in from the line. The receive filter comprised of L5 and C41, in combination with R10,
provides some rejection of out-of-band interference, such as AM broadcast signals. This interference may be coupled
from the line and would otherwise swamp the PLC device’s internal receiver circuitry. The response of the receive
filter is shown in Figure 4. Resistors R9 and R11 set the VCC/2 bias voltage required on the receive pin of the PLC
device.
Figure 4. Cypress High Voltage PLC Board Receive Filter Response
Cypress Powerline Communication Board Design Analysis
2.3 Signal Path Component Requirements
The values of the transmit filter passive components are relatively critical; 1% tolerance parts should be used to
ensure an accurate response. The opamps used in the transmit filter implementation must meet the following
requirements:
Gain Bandwidth (GBW) > 50 MHz
Voltage feedback
VDD - VSS ≥ 12 V
Power Supply Rejection Ration (PSRR) > 70 dB
Total Harmonic Distortion (THD) < -60 dB
The coupling transformer T1 must provide a low DC resistance (<0.5 ), low leakage inductance (<12 H) to
minimize signal loss and isolation, consistent with safety requirements per EN60950 specification. The signal
coupling transformer, T1, used in the CY3272 provides 3750 V isolation, a DC resistance of <0.35 and a leakage
inductance less than 1 H.
Capacitor C9 must be X1 or X2 rated to accommodate the turn-on surge, which occurs when power is applied to the
device, as well as surge immunity according to EN 61000-4-5 and EN 50065-2-1 standards. The capacitor C9, used
in the high voltage board design is a 300 V AC Panasonic ECQUG series metalized polyethylene film device, which is
rated for direct across-line application, accommodating the surge requirements of the previously mentioned
specifications.
www.cypress.com Document No. 001-55427 Rev. *E 6
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