CYPRESS CY2SSTV8575 User Manual
TV8575
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CY2SSTV8575
Differential Clock Buffer/Driver
Features
• Operating frequency: 60 MHz to 170 MHz
• Supports 266-MHz DDR SDRAM
• 5 differential outputs from 1 differential input
• Spread Spectrum comp atible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power Management Control input
• High-impedance outputs when input clock < 20 MHz
• 2.5V operation
• 32-pin TQFP JEDEC MS-026 C
Block Diagram
2
Y0
1
Y0#
12
OE
AVDD
CLK
CLK#
FBIN
FBI
#
N
23
8
5
6
21
22
Test and
Powerdown
Logic
PLL
11
15
16
27
28
30
31
18
19
Y1
Y1#
Y2
Y2#
Y3
Y3#
Y4
Y4#
FBOUT
FBOUT#
Description
The CY2SSTV8575 is a high-p erformance, low-skew , low jitt er
zero-delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTV8575 generates five
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTV8575 features differential
feedback clock outputs and inputs. This allows the
CY2SSTV8575 to be used as a zero-delay buffer.
When used as a zero-delay buffer in nested clock trees, the
CY2SSTV8575 locks onto the input reference and translates
with near zero delay to low-skew outputs.
Pin Configuration
FBIN
FBIN#
TQFP-32
VDDQ
VDDQ
VDDQ
CK
OE
JEDEC MS-026 C
Y0
FBOUT#
CK#
FBOUT
VDDQ
VSS
AVDD
Y2#
Y2
VSS
VDDQ
Y1
Y1#
VSS
9 10 11 12 13 14 15 16
AVSS
VSS
VDDQ
Y3
Y3#
VDDQ
Y4
Y4#
VSS
VSS
24 23 22 21 20 19 18 17
25
26
CY2SSTV8575
29 28 27
30
32 31
12345678
Y0#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07458 Rev. ** Revised October 30, 2002
CY2SSTV8575
Pin Description
Pin Name I/O Type Description
5,6 CLK, CLK# I L V Dif fere nti al Inpu t Differential Clock Input
21 FBIN# I Differential Input Feedback Clock Input. Connect to FBOUT# for accessing the
22 FBIN I Feedback Clock Input. Connec t to FBO UT for acces sing th e
2,12,15,27,30 Y(0:4) O Differential Outputs Clock + Outputs
1,11,16,28,31 Y(0:4)# O Clock – Outputs
18 FBOUT O Differential Outputs Feedback Clock Output. Connect to FBIN for normal
19 FBOUT# O Feedback Clock Output. Connect to FBIN# for normal
23 OE I Output Enable Input. When OE is set HIGH, all Q and Q#
3,4,7,13,20,26,29VDDQ 2.5V Nominal 2.5V Power Supply for Output Clock Buffers
PLL.
PLL.
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
outputs are enabl ed and switch at the s ame frequency as CLK.
When set LOW, all Q and Q# outpu ts are disabled (Hi-Z) and
the PLL is powered down.
8AVDD2.5V Nominal2.5V Power Supply for PLL. When AVDD is at GND, PLL is
10,14,17,24,25,32VSS 0.0V Ground Common Ground
9 AVSS 0.0V Analog Ground Analog Ground
Table 1. Function Table
INPUTS OUTPUTS PLL
AVDD OE CLK CLK# Y Y# FBOUT FBOUT#
GND H L H L H L H BYPASSED/OFF
GND H H L H L H L BYPASSED/OFF
XLLHZZZZ Off
XLHLZZZZ OFF
2.5V H L H L H L H On
2.5V H H L H L H L On
2.5V H < 20 MHz < 20 MHz Hi-Z Hi-Z Hi-Z HI-Z Off
bypassed and CLK is buffered directly to the device outputs.
During disable (OE = 0), the PLL is powered down.
Document #: 38-07458 Rev. ** Page 2 of 8
CY2SSTV8575
Power Management Functions
Output enable/disab le control of the CY2SSTV8575 allows the
user to implement power management schemes into the design. Outp uts are thre e-stated /dis abled w hen OE is as sert ed
low, see Table 1. The enabling and disabling of output s is done
in such a manner to eliminate the possibility of the partial “runt”
clocks.
Zero Delay Buffer
When used as a zero d elay buffer th e CY2SSTV8575 will lik ely
be in a nested clock tree application. For these applications
the CY2SSTV8575 offers a differential clock input pair as a
DDR _SDRAM
represents a capacitive
load
CLK
120 Ohm
CLK#
PLL
Yx
Yx#
FBIN
PLL reference. The CY2SSTV8575 can lock onto the reference and translate with near zero delay to low-skew outputs.
For normal operation, the external feedback input, FBIN, is
connected to the feedb ac k ou tpu t, FBO U T. By connecting th e
feedback output to the feedback input the propagation delay
through the device is eliminated. The PLL works to align the
output edge with tine input reference edge thus producing a
near zero delay. The reference frequency affects the static
phase offset of the PLL and thus the relative delay between
the inputs and outputs.
When AVDD is strapped LOW, the PLL is turned off and bypassed for test purposes.
= 2.5" = 0.6" (Split to Terminator)
DDR -
SDRAM
VTR
120 Ohm
VCP
120 Ohm
FBIN#
FBOUT
FBOUT#
Figure 1. Clock Structure 1
Note:
1. Output load capacitance for 2 DDR-SDRAM loads: 5 pF < CL < 8 pF.
DDR -
SDRAM
0.3"
[1]
Document #: 38-07458 Rev. ** Page 3 of 8
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