CYPRESS CY2SSTU32864 User Manual
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PRELIMINARY
Features
• Operating frequency: DC to 500 MHz
• Supports DDRII SDRAM
• Two operations modes: 25 bit (1:1) and 14 bit (1:2)
• 1.8V operation
• Fully JEDEC-compliant (JESD82-7A)
• 96-ball FBGA
Functional Description
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8V CMOS drivers that have been optimized to
drive the DDR-II DIMM load. The CY2SSTU32864 operates
from a differential clock (CK and CK#). Data are registered at
the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout
from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from
25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 = 1 and
C1 = 0 is not allowed and it will default to the C0 = C1 = 0 state.
CY2SSTU32864
1.8V, 25-bit (1:1) or 14-bit (1:2)
JEDEC-Compliant Data Registe
The device monitors both DCS# and CSR# inputs and will gate
the Qn outputs from changing states when both DCS# and
CSR# inputs are high. If either DCS# or CSR# input is low, the
Qn outputs will function normally. The RESET input has priority
over the DCS# and CSR# control and will force the outputs
low. If the DCS#-control functionality is not desired, the CSR#
input can be hardwired to ground, in which case the set-up
time requirement for DCS# would be the same as for the other
D data inputs.
The device supports low-power standby operation. When the
reset input (RESET#) is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference
voltage (VREF) inputs are allowed. In addition, when RESET#
is low, all registers are reset and all outputs are forced low. The
LVCMOS RESET# and Cn inputs must always be held at a
valid logic high or low level. To ensure defined outputs from the
register before a stable clock has been supplied, RESET#
must be held in the low state during power-up.
In the DDR-II RDIMM application, RESET# is specified to be
completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven low quickly, relative to the time to
disable the differential input receivers. However, when coming
out of reset, the register will become active quickly, relative to
the time to enable the differential input receivers.
123456
A DCKE NC VREF VDD QCKE NC
B D2 D15 GND GND Q2 Q15
CD3D16VDDVDDQ3Q16
D DODT NC GND GND QODT NC
ED5D17VDDVDDQ5Q17
F D6 D1 8 GND GND Q6 Q1 8
GNCRST#VDDVDDC1C0
H CK DCS# GND GND QCS# NC
J CK# CSR# VDD VDD ZOH ZOL
K D8 D19 GND GND Q8 Q19
LD9D20VDDVDDQ9Q20
M D10 D21 GND GND Q10 Q21
N D11 D22 VDD VDD Q11 Q22
P D12 D23 GND GND Q1 2 Q2 3
R D13 D24 VDD VDD Q13 Q24
T D14 D25 VREF VDD Q14 Q25
123456
1:1 Register C0 = 0, C1 = 0
Pin Configurations
123456
A DCKE NC VREF VDD QCK EA QCKEB
B D2 NC GND GND Q2A Q2B
CD3NCVDDVDDQ3AQ3B
D DODT NC GND GND QODT A QODTB
ED5NCVDDVDDQ5AQ5B
F D6 NC GND GND Q6A Q6 B
G NC RST# VDD VDD C1 C0
H CK DCS# GND GND QCSA# QCSB#
J CK# CSR# VDD VDD ZOH ZOL
K D8 NC GND GND Q8A Q8B
LD9NCVDDVDDQ9AQ9B
M D10 NC GND GND Q10A Q10B
N D11 NC VDD VDD Q11A Q11B
P D12 NC GND GND Q12A Q12B
R D13 NC VDD VDD Q13A Q13B
T D14 NC VREF VDD Q14A Q14B
123456
1:2 Register A C0 = 0, C1 = 1
123456
AD1NCVREFVDDQ1AQ1B
BD2NCGNDGNDQ2AQ2B
CD3NCVDDVDDQ3AQ3B
DD4NCGNDGNDQ4AQ4B
ED5NCVDDVDDQ5AQ5B
FD6NCGNDGNDQ6AQ6B
G NC RST# VDD VDD C1 C0
H CK DCS# GND GND QCSA# QCSB#
J CK# CSR# VDD VDD Z OH ZOL
KD8NCGNDGNDQ8AQ8B
LD9NCVDDVDDQ9AQ9B
M D10 NC GND GND Q10A Q10B
N DODT NC VDD V DD QODTA QODT B
P D12 NC GND GND Q12A Q12B
R D13 NC VDD VDD Q13A Q13B
T DCKE NC VREF VDD QCKEA QCKEB
123456
1:2 Register B C0 = 1, C1 = 1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07576 Rev. *D Revised March 29, 2005
PRELIMINARY
Pin Definitions
Pin Name
GND B3, B4, D3, D4, F3, F4,
VDD A4, C3, C4, E3, E4, G3,
VREF A3, T3 A3, T3 A3, T3 Input Reference Voltage
ZOHJ5 J5J5Reserved
ZOLJ6 J6J6Reserved
CK H1 H1 H1 Positive Master Clock
CK# J1 J1 J1 Negative Master Clock
C0 G6 G6 G6 Configuration Control Input
C1 G5 G5 G5 Configuration Control Input
RESET# G2 G2 G2 Asynchronous Reset – resets registers and
CSR# J2 J2 J2 Chip Select – Disables D1-D24 when both CSR#
DCS# H2 H2 H2 Chip Select – Disables D1-D24 when both CSR#
D1
D2-3 B1, C1 B1, C1 B1, C1 Data Input – clocked in on the crossing points of
D4
D5, 6, 8, 9, 10E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data Input – clocked in on the crossing points of
D11 N1 N1
D12, 13 P1, R1 P1, R1 P1, R1 Data Input – clocked in on the crossing points of
D14 T1 T1
D15-25 B2, C2, E2, F2, K2, L2,
DODT D1 D1 N1 The outputs of this register bit will not be
DCKE A1 A1 T1 The outputs of this register bit will not be
Q1A
Q2A–3A B5, C5 B5, C5 B5, C5 Data Outputs that are suspended by the DCS#
Q4A
Q5A, 6A, 8A,
9A, 10A
Q11A N5 N5
Pin Number
(C0 = 0, C1 = 0)
H3, H4, K3, K4, M3, M4,
P3, P4
G4, J3, J4, L3, L4, N3,
N4, R3, R4, T4
M2, N2, P2, R2, T2
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#
Pin Number
(C0 = 0, C1 = 1)
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
Pin Number
(C0 = 1, C1 = 1) Description
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A1 Data Input – clocked in on the crossing points of
D1 Data Input – clocked in on the crossing points of
A5 Data Outputs that are suspended by the DCS#
D5 Data Outputs that are suspended by the DCS#
Ground
Power Supply Voltage
disables Vref data and clock differential input
receivers
and DCS# are High (VDD)
and DCS# are High (VDD)
CK and CK#
CK and CK#
CK and CK#
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
Data Input – clocked in on the crossing points of
CK and CK#
suspended by the DCS# and CSR# Control
suspended by the DCS# and CSR# Control
and CSR# control
and CSR# control
and CSR# control
and CSR# control
CY2SSTU32864
Document #: 38-07576 Rev. *D Page 2 of 10
PRELIMINARY
CY2SSTU32864
Pin Definitions (continued)
Pin Name
Q12A, Q13A P5, R5 P5, R5 P5, R5
Q14A T5 T5
Q1B
Q2B-3B
Q4B
Q5B, 6B, 8B,
9B, 10B,
Q11B
Q12B, 13B
Q14B
Q15–25 B6, C6, E6, F6, K6, L6,
QCSA# H5 H5 H5 Data outputs that will not be suspended by the
QCSB#
QODTA D5 D5 N5 Data outputs that will not be suspended by the
QODTB
QCKEA A5 A5 T5 Data outputs that will not be suspended by the
QCKEB
NC A2, A6, D2, D6, G1, H6 A2, B2, C2, D2,
Pin Number
(C0 = 0, C1 = 0)
M6, N6, P6, R6, T6
Pin Number
(C0 = 0, C1 = 1)
B6, C6 B6, C6 Data Outputs that are suspended by the DCS#
E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS#
N6 Data Outputs that are suspended by the DCS#
P6, R6 P6, R6 Data Outputs that are suspended by the DCS#
T6 Data Outputs that are suspended by the DCS#
H6 H6 Data outputs that will not be suspended by the
D6 N6 Data outputs that will not be suspended by the
A6 T6 Data outputs that will not be suspended by the
E2, F2, G1, K2, L2,
M2, N2, P2, R2, T2
Pin Number
(C0 = 1, C1 = 1) Description
Data Outputs that are suspended by the DCS#
and CSR# control
A6 Data Outputs that are suspended by the DCS#
D6 Data Outputs that are suspended by the DCS#
A2, B2, C2, D2,
E2, F2, G1, K2, L2,
M2, N2, P2, R2, T2
and CSR# control
and CSR# control
and CSR# control
and CSR# control
and CSR# control
and CSR# control
and CSR# control
Data Outputs that are suspended by the DCS#
and CSR# control
DCS# and CSR# control
DCS# and CSR# control
DCS# and CSR# control
DCS# and CSR# control
DCS# and CSR# control
DCS# and CSR# control
No Connect Pins
Document #: 38-07576 Rev. *D Page 3 of 10
PRELIMINARY
Table 1. Flip Flop Function Table
Inputs Outputs
RESET# DCS# CSR# CK CK# Dn, DODT, DCKE Qn QCS# QODT, QCKE
HL L L LLL
HL L H HLH
H L L L or H L or H X Q0 Q0 Q0
HL H L LLL
HL H H HLH
H L H L or H L or H X Q0 Q0 Q0
HH L L LHL
HH L H HHH
H H L L or H L or H X Q0 Q0 Q0
HH H L Q0HL
HH H H Q0HH
H H H L or H L or H X Q0 Q0 Q0
L X or Floating X or Floating X or Floating X or Floating X or Floating L L L
CY2SSTU32864
Document #: 38-07576 Rev. *D Page 4 of 10
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