CYPRESS CY2DP3120 User Manual

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FastEdge™ Series

CY2DP3120

1:20 Differential Clock/Data Fanout Buffe

Features

• Twenty ECL/PECL differential outputs

• One ECL/PECL compatible differential or single-ended
clock inputs

• One HSTL compatible differential or single-ended clock
inputs

• Hot-swappable/-insertable

• 50 ps output-to-output skew

• 150 ps device-to-device skew

• 500 ps propagation delay (typical)

• 1.4 ps RMS period jitter (max.)

• 1.5 GHz Operation (2.7 GHz max. toggle frequency)

• PECL mode supply range: V

EE

= 0V

with V

• ECL mode supply range: V
with V

CC

= 0V

• Industrial temperature range: –40°C to 85°C

• 52-pin 1.4-mm TQFP package

• Temperature compensation like 100K ECL

• Pin compatible with MC100ES6221

= 2.5V± 5% to 3.3V±5%

CC

= –2.5V± 5% to –3.3V±5%

E E

Functional Description

The CY2DP3120 is a low-skew, low propagation delay 1-to-20
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.

The device features two differential input paths that are multi­plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP3120 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on
ECL/PECL signal to twenty ECL/PECL differential loads. An
external bias pin, VBB, is provided for this purpose. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to ground via a

0.01-µF capacitor. Traditionally, in ECL, it is used to provide
the reference level to a receiving single-ended input that might
have a different self-bias point.

Since the CY2DP3120 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP3120 delivers consistent performance
over various platforms.

Block Diagram

VCC

CLKA

CLKA#

VEE

VCC

CLKB

CLKB#

CLK_SEL

VEE

VEE

Q0
Q0#

Q19
Q19#

VBB

Pin Configuration

Q0Q1Q0#

Q1#Q2Q2#Q3Q3#Q4Q4#Q5Q5#

49

48

5152

VCC

VCC

CLK_SEL

CLKA

CLKA#

VBB

CLKB

CLKB#

VEE

Q19#

Q19

Q18#

Q18

50

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VCC

15

Q17#

CY2DP3120

17

16

Q17

Q16#

18

Q16

VCC

434445

4647

2019

Q15

Q14

Q15#

Q14#

40

4142

232221

Q13

Q13#

Q6

39

Q6#

38

Q7

37

Q7#

36

Q8

35

Q8#

34

Q9

33

Q9#

32

31

Q10

Q10#

30

29

Q11

28

Q11#

27

VCC

26

2524

Q12

Q12#

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-07514 Rev.*C Revised July 28, 2004

FastEdge™ Series

CY2DP3120

Pin Definitions

[1, 2, 3]

Pin Name I/O Type Description

3 CLK_SEL I,PD ECL/PECL/HSTL Input clock select

4 CLKA, I,PD ECL/PECL Differential input clocks

6 VBB

[3]

OBias Reference voltage output

5 CLKA# I,PD/PU ECL/PECL Differential input clocks

7 CLKB, I,PD HSTL Alternate differential input clocks

8 CLKB# I,PD/PU HSTL Alternate differential input clocks

9 VEE

[2]

-PWR Power Negative supply

1,2,14,27,40 VCC +PWR Power Positive Supply

52,50,48,46,44,42,39,37,

Q(0:19) O ECL/PECL True output
35,33,31,29,26,24,22,20,
18,16,13,11

51,49,47,45,43,41,38,36,

Q#(0:19) O ECL/PECL Complement output
34,32,30,28,25,23,21,19,
17,15,12,10

Table 1.

Control Operation

CLK_SEL

0 CLKA, CLKA# input pair is active (Default condition with no connection to pin)

CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations

1 CLKB, CLKB# input pair is active.

CLKB can be driven with HSTL-compatible signals with respective power configurations

Governing Agencies

The following agencies provide specifications that apply to the
CY2DP3120. The agency name and relevant specification is
listed below in Tab l e 2.

Table 2.

Agency Name Specification

JEDEC JESD 020B (MSL)

JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)

Mil-Spec 883E Method 1012.1 (Thermal Theta JC)

Notes:

1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power

2. In ECL mode (negative power supply mode), V
V

is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)

EE

and are between V

is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).

3. V

BB

and VEE.

CC

is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode),

EE

Document #: 38-07514 Rev.*C Page 2 of 9

FastEdge™ Series

CY2DP3120

Absolute Maximum Ratings

Parameter Description Condition Min. Max. Unit

V

CC

V

EE

T

S

T

J

ESD

h

M

SL

Gate Count Total Number of Used Gates Assembled Die 50 gates

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

Operating Conditions

Parameter Description Condition Min. Max. Unit

I

BB

LU

I

T

A

Ø

Jc

Ø

Ja

I

EE

C

IN

L

IN

V

IN

V

TT

V

OUT

I

IN

Positive Supply Voltage Non-Functional –0.3 4.6 V

Negative Supply Voltage Non-Functional -4.6 0.3 V

Temperature, Storage Non-Functional –65 +150 °C

Temperature, Junction Non-Functional 150 °C

ESD Protection Human Body Model 2000 V

Moisture Sensitivity Level 3 N.A.

Output Reference Current Relative to V

BB

|200| uA

Latch Up Immunity Functional, typical 100 mA

Temperature, Operating Ambient Functional –40 +85 °C

Dissipation, Junction to Case Functional 22

Dissipation, Junction to Ambient Functional 60

Maximum Quiescent Supply Current VEE pin 250

[4]

[4]

[5]

°C/W

°C/W

mA

Input pin capacitance 3pF

Pin Inductance 1nH

Input Voltage Relative to V

Output Termination Voltage Relative to V

Output Voltage Relative to V

Input Current (ECL,PECL and HSTL)

[7]

VIN = VIL, or VIN = V

CC

CC

CC

[6]

[6]

[6]

IH

–0.3 V

V

– 2 V

CC

–0.3 V

+ 0.3 V

CC

+ 0.3 V

CC

l150l uA

PECL/HSTL DC Electrical Specifications

Parameter Description Condition Min. Max. Unit

V

CC

V

CMR

V

X

V

OH

V

OL

V

IH

V

IL

[3]

V

BB

Notes:

4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1

5. Power Calculation: V

6. where V

7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.

8. Refer to Figure 1

(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input

9. V

X

swing lies within the V

10. Equivalent to a termination of 50Ω
will operate down to VEE; VIH will operate up to V

11. V

IL

Operating Voltage 2.5V ± 5%, VEE = 0.0V

3.3V ± 5%, V

PECL Input Differential Crosspoint

[8]

Voltage

HSTL Input Differential Crosspoint Volt-

[9]

age

Differential operation 1.2 V

Standard Load Differential
Operation

Output High Voltage IOH = –30 mA

Output Low Voltage
V

= 3.3V ± 5%

CC

V

= 2.5V ± 5%

CC

I

= –5 mA

OL

EE

[10]

[10]

= 0.0V

Input Voltage, High Single-ended operation V

Input Voltage, Low Single-ended operation V

Output Reference Voltage Relative to V

* IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip.

is 3.3V±5% or 2.5V±5%

CC

CC

(AC) specification. Violation of VX(AC) or V

DIF

to VTT. I

OHMIN

=(V

OHMIN-VTT

CC

)/50; I

DIF

(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Fig. 2.

=(V

OHMAX

[6]

CC

OHMAX-VTT

)/50; I

OLMIN

2.375

3.135

0.68 0.9 V

V

– 1.25 V

CC

V

=(V

OLMIN-VTT

– 1.995

CC

V

–1.995

CC

– 1.165 V

CC

V

CC

CC

– 1.945

[11]

– 1.620 VCC – 1.220 V

)/50; I

OLMAX

V
V

CC

V

CC

=(V

OLMAX-VTT

2.625

3.465

CC

– 0.7 V

CC

– 1.5

CC

– 1.3

CC

– 0.880

[11]

– 1.625 V

)/50;

V
V

V

V
V

V

Document #: 38-07514 Rev.*C Page 3 of 9