CYPRESS CY28RS400 User Manual
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CY28RS400
Clock Generator for ATI RS400 Chipset
Features
• Supports Intel CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 48-MHz USB clock
• 33-MHz PCI clock
Block Diagram
XOUT
CPU_STP#
CLKREQ[0:1]#
FS_[C:A]
VTT_PWRGD#
IREF
SDATA
SCLK
XIN
PD
PLL1
PLL2
Logic
XTAL
OSC
I2C
PLL Ref Freq
Divider
Network
VDD_REF
REF[0:2]
VDD_CPU
CPUT[0:2], CPUC[0:2],
VDD_SRC
SRCT[0:5],SRCC[0:5]
VDD_SRCS
SRCST[0:1],SRCSC[0:1]
VDD_PCI
PCI
VDD_48 MHz
USB_48
VTT_PWRGD#/PD
• Low-voltage frequency select input
2
•I
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU SRC PCI REF USB_48
x3 x8 x1 x 3 x 1
Pin Configuration
Xin
XOUT
VDD_48
USB_48
VSS_48
SCLK
SDATA
FSC
CLKREQ#0
CLKREQ#1
SRCT5
SRCC5
VDD_SRC
VSS_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
SRCST1
SRCSC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CY28RS400
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
VSS_REF
REF0/FSA
REF1/FSB
REF2
VDD_PCI
PCI0/409_410
VSS_PCI
CPU_STOP#
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
CPUT2
CPUC2
VDDA
VSSA
IREF
VSS_SRC1
VDD_SRC1
SRCT0
SRCC0
VDD_SRCS
VSS_SRCS
SRCST0
SRCSC0
56 SSOP/TSSOP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07637 Rev. *B Revised October 19, 2004
CY28RS400
Pin Description
Pin No. Name Type Description
47,46,43,42,
41,40
50 PCI0/409_410 I/O,PD33-MHz clock output/CPU Frequency table Select
37 IREF I A precision resistor attached to this pin is connected to the internal current reference.
54 REF0/ FSA I/O, SE, 14.318MHz REF clock ouput/ CPU Frequency Select. Intel
53 REF1/FSB I/O, SE 14.318MHz REF clock ouput
52 REF2 O, SE 14.318MHz REF clock ouput. Intel Type-5 buffer.
7 SCLK I,PU SMBus-compatible SCLOCK.This pin has an internal pullup, but is tri-stated in power-down.
8 SDATA I/O, PU SMBus compatible SDATA.This pin has an internal pullup, but is tri-stated in power-down.
27, 28, 30, 29 SRCST/C[1:0] O, DIF Differential Selectable Serial reference clock. Intel Type-X buffer. Includes overclock
12, 13, 16,
17, 18, 19,
22, 23, 24, 25
,34,33
10,11 CLKREQ#[0:1] I, SE, PDOutput Enable control for SRCT/C. Output enable control required by Minicard
4 USB_48 O, SE 48-MHz clock output. Intel Type-3A buffer.
6 VTT_PWRGD#/PD IPD3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
48 CPU_STP# I, PU 3.3V LVTTL input. This pin is used to gate the CPU outputs. CPU outputs are turned
9 FSC I 3.3V LVTTL input. CPU Clock Frequency Select
3 VDD_48 PWR 3.3V power supply for USB outputs
45 VDD_CPU PWR 3.3V power supply for CPU outputs
51 VDD_PCI PWR 3.3V power supply for PCI outputs
56 VDD_REF PWR 3.3V power supply for REF outputs
14, 21 VDD_SRC PWR 3.3V power supply for SRC outputs
35 VDD_SRC1 PWR 3.3V power supply for SRC outputs
32 VDD_SRCS PWR 3.3V power supply for SRCS outputs
39 VDDA PWR 3.3V Analog Power for PLLs
5 VSS_48 GND Ground for USB outputs
44 VSS_CPU GND Ground for CPU outputs
49 VSS_PCI GND Ground for PCI outputs
55 VSS_REF GND Ground for REF outputs
15, 20, 26 VSS_SRC GND Ground for SRC outputs
36 VSS_SRC1 GND Ground for SRC outputs
31 VSS_SRCS GND Ground for SRCS outputs
38 VSSA GND Analog Ground
1 XIN I 14.318-MHz Crystal Input
2 XOUT O 14.318-MHz Crystal Output
CPUT/C[2:0] O, DIF Differential CPU clock output.
Intel Type-X buffer.
Intel Type-5 buffer.
0 = 410 frequency select table
1 = 409 frequency select table.
This has an internal pull-down
Type-5 buffer.
/ CPU Frequency Select. Intel Type-5 buffer.
support through SMBUS
SRCT/C[5:0] O, DIF 100 MHz Differential Serial reference clock. Intel Type-X buffer.
specification. These pins have an internal pull-down.
0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled
FS_C and 409_410 inputs. After asserting VTT_PWRGD# (active low), this pin
becomes a realtime input for asserting power down (active high)
off two cycles after assertion of this pin
Document #: 38-07637 Rev. *B Page 2 of 19
CY28RS400
Frequency Select Pins (FS_A, FS_B, FS_C and
409_410)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C and 409_410
inputs prior to VTT_PWRGD# assertion (as seen by the clock
synthesizer). Upon VTT_PWRGD# being sampled low by the
clock chip (indicating processor VTT voltage is stable), the
clock chip samples the FS_A, FS_B, FS_C and 409_410 input
values. For all logic levels of FS_A, FS_B, FS_C and 409_410
VTT_PWRGD# employs a one-shot functionality in that once
Table 1. Frequency Select Table (FS_A FS_B FS_C) 410 mode, 409_410 = 0
FS_C FS_B FS_A CPU SRC PCIF/PCI REF0 USB
1 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz
0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz
0 1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz
0 0 0 266 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz
1 1 1 Reserved 100 MHz 33 MHz 14.318 MHz 48 MHz
Table 2. Frequency Select Table (FS_A FS_B) 410 mode, 409_410 = 1
FS_B FS_A CPU SRC PCIF/PCI REF0 USB
0 0 100 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz
0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz
1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz
a valid low on VTT_PWRGD# has been sampled, all further
VTT_PWRGD#, FS_A, FS_B, FS_C and 409-410 transitions
will be ignored. There are 2 CPU frequency select tables. One
based on the CK409 specifications and one based on the
CK410 specifications. The table to be used is determined by
the value latched on the PCI0/409_410 pin by the
VTT_PWRGD/PD# pin. A '0' on this pin selects the 410
frequency table and a '1' on this pin selects the 409 frequency
table. In the 409 table, only the FS_A and FS_B pins influence
the frequency selection.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Table 3. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:5) Chip select address, set to ‘00’ to access device
(4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1 Start 1 Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Tab le 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Document #: 38-07637 Rev. *B Page 3 of 19
CY28RS400
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
27:20 Byte Count – 8 bits 20 Repeat start
28 Acknowledge from slave 27:21 Slave address – 7 bits
36:29 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits
.... Data Byte N –8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave – 8 bits
.... NOT Acknowledge
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte – 8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address – 7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave – 8 bits
38 NOT Acknowledge
39 Stop
Document #: 38-07637 Rev. *B Page 4 of 19
Control Registers
Byte 0:Control Register 0
Bit @Pup Name Description
7 1 SRC[T/C]5 SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6 1 SRC[T/C]4 SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
5 1 SRC[T/C]3 SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4 1 SRC[T/C]2 SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3 1 SRC[T/C]1 SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
2 1 SRC [T/C]0 SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1 1 SRCS[T/C]1 SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 1 SRCS[T/C]0 SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 REF2 REF2 Output Enable
0 = Disable, 1 = Enable
6 1 REF1 REF1 Output Enable
0 = Disable, 1 = Enable
5 1 REF0 REF0 Output Enable
0 = Disable, 1 = Enable
4 1 PCI0 PCI0 Output Enable
0 = Disable, 1 = Enable
3 1 USB_48 USB_48MHz Output Enable
0 = Disable, 1 = Enable
2 1 CPU[T/C]2 CPU[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1 1 CPU[T/C]1 CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 1 CPU[T/C]0 CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CY28RS400
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 CPUT/C
SRCT/C
6 1 USB_48 48MHz Output Drive Strength
5 1 PCI 33MHz Output Drive Strength
4 0 Reserved Reserved
3 1 Reserved Reserved
20 CPU
SRC
1 1 Reserved Reserved
Document #: 38-07637 Rev. *B Page 5 of 19
Spread Spectrum Selection
‘0’ = -0.35%
‘1’ = -0.50%
0 = 1x, 1 = 2x
0 = 1x, 1 = 2x
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2 (continued)
Bit @Pup Name Description
0 1 Reserved Reserved
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 CLKREQ# CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
6 0 CPU CPU pd drive mode
0 = CPU clocks driven when power down, 1 = CPU clocks tri-state
5 1 SRC SRC pd drive mode
0 = SRC clocks driven when power down, 1 = SRC clocks tri-state
4 0 CPU CPU_STOP# drive mode
0 = CPU clocks driven , 1 = CPU clocks tri-state
3 1 CPU2 Allow control of CPU2 with CPU_STOP#
0 = CPU2 is free running, 1 = CPU2 is stopped with CPU_STOP#
2 1 CPU1 Allow control of CPU1 with CPU_STOP#
0 = CPU1 is free running, 1 = CPU1 is stopped with CPU_STOP#
1 1 CPU0 Allow control of CPU0 with CPU_STOP#
0 = CPU0 is free running, 1 = CPU0 is stopped with CPU_STOP#
0 1 Reserved Reserved
CY28RS400
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#0 control
5 0 SRC[T/C]3 SRC[T/C]3 CLKREQ#0 control
4 0 SRC[T/C]2 SRC[T/C]2 CLKREQ#0 control
3 0 SRC[T/C]1 SRC[T/C]1 CLKREQ#0 control
2 0 SRC[T/C]0 SRC[T/C]0 CLKREQ#0 control
1 1 Reserved Reserved
0 1 Reserved Reserved
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ#1 control
6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#1 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
1 = SRC[T/C]5 stoppable by CLKREQ#1 pin
0 = SRC[T/C]5 free running
1 = SRC[T/C]4 stoppable by CLKREQ#1 pin
0 = SRC[T/C]4 free running
Document #: 38-07637 Rev. *B Page 6 of 19
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