CYPRESS CY26049-22 User Manual
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CY26049-22
FailSafe™ PacketClock™
Global Communications Clock Generato
Features
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• 100-MHz output from 10-MHz input
• Low-jitter, high-accuracy outputs
• 3.3V ± 5% operation
• 16-lead TSSOP
Logic Block Diagram
external pullable crystal
(10MHz)
IN
input reference
(10MHz)
ICL K
FAILSAFE
CONTROL
TM
DIGITAL
CONTROLLED
CRYSTAL
OSCILLATOR
Benefits
• Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external
loop filter components
• When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• Works with commonly available, low-cost 10-MHz crystal
• Zero-ppm error for all output frequencies
• Compatible across industry standard design platforms
• Industry standard package with 6.4 × 5.0 mm
a height profile of just 1.1 mm
XOUT
PHASE
LOCKED
LOOP
OUTPUT
DIVIDER
CLKA
100MHz
2
footprint and
SAFE
ICL K d ete cte d
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07730 Rev. ** Revised January 12, 2005
Pin Configuration
16-pin TSSOP
Top V iew
ICLK 1 16 NC
NC 2 15
NC
3 14 NC
NC 4 13 NC
VDD 5 12 VDD
VSS 6 11 VSS
NC 7 10 SAFE
XIN 8 9 XOUT
CLKA
Pin Description
Pin Number Pin Name Pin Description
1ICLKReference Input Clock; 10 MHz.
2NC No Connect.
3NCNo Connect.
4NCNo Connect.
5VDDVoltage Supply; 3.3V.
6VSSGround.
7NCNo Connect
8XINPullable Crystal Input; 10 MHz.
9XOUTPullable Crystal Output; 10 MHz.
10 SAFE High = reference ICLK within range, Low = reference ICLK out of range.
11 VS S Ground.
12 VDD Voltage Supply; 3.3V.
13 NC No Connect.
14 NC No Connect.
15 CLKA Clock Output. 100 MHz
16 NC No Connect.
CY26049-22
Selector Guide
Part Number Input Frequency Range Outputs Output Frequencies
CY26049ZXC-22 Reference Input Clock: 10 MHz
Crystal: 10-MHz pullable Crystal per Cypress Specification
Description
CY26049-22 is a FailSafe frequency synthesizer with a
reference clock input and 100-MHz output. The device
provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure. The continuous, glitch-free operation is achieved by
using a DCXO, which serves as a primary clock source. The
FailSafe control circuit synchronizes the DCXO oscillator with
the reference as long as the reference is within the pull range
of the crystal.
Document #: 38-07730 Rev. ** Page 2 of 6
In the event of a reference clock failure the DCXO maintains
the last frequency of the reference clock. The unique feature
of the CY26049-22 is that the DCXO is, in fact, the primary
clocking source. When the reference clock is restored, the
DCXO automatically resynchronizes to the reference. The
status of the reference clock input, as detected by the
CY26049-22, is reported by the SAFE pin.
1 100 MHz
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