Cypress CY25822-2 User Manual

CK-SSC Spread Spectrum Clock Generato

r

2

Features

• 3.3V operation

• 48- and 66-MHz frequency support

• Selectable slew rate control

• 350-pS jitter

2

•I

C programmability

• 500-µA power-down current

• Spread Spectrum for best electro magnetic interference
(EMI) reduction

• 8-pin SOIC package

CY25822-

Block Diagram

Clock Input

SDATA

SCLOCK

PWRDWN#

Pin Configuration

Freq. Phase

M

Logic

Control

Detector

Feedback

Divider

CLKIN

N

VDD

GND

Charge

Pump

1

2

CY 25822-2

3

VDD

GND

Σ

Modulating

Waveform

PLL

8

*PW RD WN#

7

SCLOCK

SDATA

6

VCO

DividersDivider

Post

REFOUT

CLKOUT

(SSCG Output)

CLKOUT

4

* 150KΩ P ull-up

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

5

REFOUT

Document #: 38-07531 Rev. ** Revised March 18, 2003

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Pin Description

Pin No. Pin Name Pin Type Pin Description

1 CLKIN Input 48-MHz or 66-MHz Clock Input.
2 VDD Power Power Supply for PLL and Outputs.
3 GND Ground Ground for Outputs.
4 CLKOUT Output 48-MHz or 66-MHz Spread Spectrum Clock Output.
5REFOUTOutput Non-spread Spectrum Reference Clock Output.

2

6 SDATA I/O I
7 SCLOCK Input I
8 PWRDWN# Output LVTTL Input for PowerDown# Active Low.

C-compatible SDATA.

2

C-compatible SCLOCK.

CY25822

Serial Data Interface

T o enha nce the flexibi lity and functi on of the clock sy nthesizer ,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled.

The registers associated with the Serial Data Interface
initializes to thei r defa ult s etting upon pow er-up, a nd th erefore
use of this interfac e is option al. Clo ck de vice regis ter cha nges
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.

Ta ble 1. Command Code Definition

Bit Description

7 0 = Block read or block write operation

1 = Byte read or byte write operation

(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be ’0000000’

Table 2. Block Read and Block Write Protocol

Block Write Protocol Block Read Protocol

Bit Description Bit Description

1Start 1Start

2:8 Slave address – 7 bits 2:8 Slave address – 7 bits

9 Write = 0 9 Write = 0

10 Acknowledge from slave 10 Acknowledge from slave

11:18 Command Code – 8 bits

'00000000' stands for block operation

19 Acknowledge from slave 19 Acknowledge from slave

20:27 Byte Count – 8 bits 20 Repeat start

28 Acknowledge from slave 21:27 Slave address – 7 bits

29:36 Data byte 1 – 8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

38:45 Data byte 2 – 8 bits 30:37 Byte count from slave – 8 bits

46 Acknowledge from slave 38 Acknowledg e

.... ...................... 39:46 Data byte from slave – 8 bits

.... Data Byte (N–1) –8 bits 47 Acknowledge

.... Acknowledge from slave 48:55 Data byte from slave – 8 bits

Data Protocol

The clock driver serial protocol accepts byte write, byte read,
block write, and blo ck read op eration from the c ontrol ler. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte rea d o pera tio ns , th e
system controller can access individual indexed bytes. The
offset of the indexe d byte is encoded in the command co de, as
described in Table 1.

The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol.The s lave receive r addre ss i s 110101 00 (D 4h).

11:18 Command Code – 8 bits

'00000000' stands for block operation

Document #: 38-07531 Rev. ** Page 2 of 9

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Table 2. Block Read and Block Write Protocol (continued)

.... Data Byte N –8 bits 56 Acknowledge

.... Acknowledge from slave .... Data bytes from slave/Acknowledge

.... Stop .... Data byte N from slave – 8 bits

.... Not Acknowledge

.... Stop

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol Byte Read Protocol

Bit Description Bit Description

1Start 1Start

2:8 Slave address – 7 bits 2:8 Slave address – 7 bits

9 Write = 0 9 Write = 0

10 Acknowledge from slave 10 Acknowledge from slave

11:18 Command Code – 8 bits

'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed

19 Acknowledge from slave 19 Acknowledge from slave

20:27 Data byte from master – 8 bits 20 Repeat start

28 Acknowledge from slave 21:27 Slave address – 7 bits
29 Stop 28 Read = 1

11:18 Command Code – 8 bits

'1xxxxxxx' st ands fo r byte op eration, bits [6:0]
of the command code represents the offset of
the byte to be accessed

29 Acknowledge from slave

30:37 Data byte from slave – 8 bits

38 Not Acknowledge
39 S top

CY25822

Byte 0: Control Register

Bit @Pup Pin# Name Pin Description

714SS0 –
604SS1 –
504SS2 –
404SS3 –
3 1 Not Applicable Reserved, must be written as 1
214, 5CLKOUT,

REFOUT

1 1 4 CLKOUT Spread Spectrum enable

0 0 Not Applicable No Pins

Ta ble 4. Spread Spectrum Select

SS3 SS2 SS1 SS0 Spread Mode Spread Amount%

0 0 0 0 Down 0.8
0 0 0 1 Down 1.0
0 0 1 0 Down 1.25
0 0 1 1 Down 1.5
0 1 0 0 Down 1.75

Power-down three-state enable
0 = three-state outputs, 1 = drive outputs low
(Applies only in Power Down State)

0 = spread off, 1 = spread on

Document #: 38-07531 Rev. ** Page 3 of 9

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