CYPRESS CY25701JXC, CY25701FJXC User Manual

CY25701JXC/FJXC

Programmable High-Frequency Crystal Oscillator with Spread

Spectrum (SSXO) and No-Spread Spectrum (XO) Option

Features

• Crystal Oscillator with Spread Sp ectrum Clock (SSXO)

• No-Spread Spectrum (XO) Option

• Wide operating output clock frequency range of
10–166 MHz

• Programmable spread spectrum with nominal 31.5-kHz
modulation frequency

• Center spread: ±0.25% to ±2.0%

• Down spread: –0.5% to –4.0%

• No spread: ± 0.0%

• Integrated phase-locked loop (PLL)

• 85 ps typical cycle-to-cycle Jitter with SSCLK = 133MHz

• 3.3V operation

• Output Enable function

• Package available in 4-pin Plastic JE

• Pb-free package

Logic Block Diagram

RFB

Benefits

• Provides wide range of spread percentages for
maximum electromagnetic interference (EMI)
reduction, to meet regulatory agency electromagnetic
compliance (EMC) requirements. Reduces devel­opment and manufacturing costs and time-to-market.

• This versatile programming feature enables the users
to switch between SSXO (with Spread) and XO (without
Spread) functions with ease.

• Internal PLL to generate up to 166-MHz output.

• Suitable for most PC, consumer, and networking
applications

• Application compatibility in standard and low-power
systems

• In-house programming of samples and prototype
quantities is available using the CY3672 programming
kit and CY3613 (JEC package) socket adapters.
Production quantities are available through Cypress’
value-added distribution partners or by using
third-party programmers from BP Microsystems, HiLo
Systems, and others.

Pin Configuration

CY25701JXC/FJXC

4-pin Plastic JE

PLL
with

OE

MODULATION

CONTROL

CXIN

PROGRAMMABLE

CONFIGURATION

XOUT

C

1

4 2

VDD VSS

OUTPUT

DIVIDERS

and

MUX

3

SSCLK

1

OE

2

VSS

SSCLK

VDD

4

3

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-07684 Rev. *E Revised March 27, 2006

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CY25701JXC/FJXC

Pin Definition

Pin Name Description

1OE Output Enable pin: Active HIGH. If OE = 1, SSCLK is enabled.
2 VSS Power supply ground.
3 SSCLK Spread spectrum clock output (with or without spread).
4VDD3.3V power supply.

Functional Description

The CY25701JXC/FJXC is a Spread Spectrum Crystal Oscil­lator (SSXO) IC used for the purpose of reducing EMI found in
today’s high-speed digital electronic systems.

The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the embedded input crystal. By frequency
modulating the clock, the measured EMI at the fundamental
and harmonic frequencies are greatly reduced. This reduction
in radiated energy can significantly reduce the cost of
complying with regulatory agency (EMC) requirements and
improve time-to-market without degrading system perfor­mance.

The CY25701JXC/FJXC uses a programmable configuration
memory array to synthesize output frequency and spread%.

The spread% is programmed to either center spread or down
spread with various spread percentages. The range for center
spread is from ±0.25% to ±2.00%. The range for down spread
is from –0.5% to –4.0%. Contact the factory for smaller or
larger spread% amounts if required. Refer to Table 2 for
spread selection and no-spread values.

The frequency modulated SSCLK output can be programmed
from 10–166 MHz.

The CY25701JXC/FJXC is available in a 4-pin plastic package
with operating temperature range of –20 to 70°C.

Table 1. Programming Data Requirement

Pin Function Output Frequency Spread Percent Code

Pin Name SSCLK SSCLK SSCLK

Pin# 3 3 3

Units MHz % kHz

Program Value ENTER DATA ENTER DATA 31.5

Programming Description

Field/Factory-Programmable CY25701JXC/FJXC

Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (FAE) or sales representative. Once the request has
been processed, you will receive a new part number, samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.

Additional information on the CY25701JXC/FJXC can be
obtained from the Cypress web site at www.cypress.com.

Output Frequency, SSCLK Output (SSCLK, pin 3)

The modulated frequency at the SSCLK output is pr oduced by
synthesizing from the embedded crystal oscillator frequency
input. The range of synthesized clock is from 10–166 MHz.

Spread Percentage (SSCLK, pin 3)

The SSCLK spread can be programmed to various spread
percentage values from ±0.25% to ±2.0% for Center Spread
and from –0.5% to –4.0% for Down Spread. Refer to Table 2
for available spread options. Enter ±0.0% (No spread) for XO
(Crystal Oscillator) without spread option.

Frequency Modulation (SSCLK, pin 3)

The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 10 to 166 MHz. Contact the factory
if a higher-modulation frequency is required.

[1]

Frequency Modulation

Table 2. Spread Percent Selection

Center Spread Code A B C D E F Z

Percentage ±0.25% ±0.5% ±0.75% ±1.0% ±1.5% ±2.0% ±0.0%

Down Spread Code G H J K L M Z

Percentage –0.5% –1.0% –1.5% –2.0% –3.0% –4.0% ±0.0%

Note:

1. ±0.0% or Code “Z” for XO (No-Spread) option.

Document #: 38-07684 Rev. *E Page 2 of 7

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CY25701JXC/FJXC

Absolute Maximum Rating

Supply Voltage (VDD)....................................–0.5V to +7.0V

DC Input Voltage....................................–0.5V to V

DD

+ 0.5V

Storage Temperature (Non-condensing) .... –55°C to +100°C

Junction Temperature................................ –40°C to +125°C

Data Retention @ Tj = 12 5°C................................> 10 years

Package Power Dissipation......................................350 mW

Operating Conditions

Parameter Description Min. Typ. Max. Unit

V

DD

T

A

C

LOAD

F

SSCLK

F

MOD

T

PU

Supply Voltage 3.00 3.30 3.60 V
Ambient Temperature –20 – 70 °C
Max. Load Capacitance @ pin 3 – – 15 pF
SSCLK output frequency, C

= 15 pF 10 – 166 MHz

LOAD

Spread Spectrum Modulation Frequency 30.0 31.5 33.0 kHz
Power-up time for VDD to reach minimum specified voltage (power ramp must

0.05 – 500 ms

be monotonic)

DC Electrical Characteristics

Parameter Description Condition Min. T yp. Max. Unit

I

OH

I

OL

V

IH

V

IL

I

IH

I

IL

I

OZ

[2]

C

IN

I

VDD

∆fAging T

Output High Current (pin 3) VOH = VDD – 0.5, V

= 3.3V (source) 10 12 – mA

DD

Output Low Current (pin 3) VOL = 0.5, VDD= 3.3V (sink) 10 12 – mA
Input High Voltage (pin 1) CMOS levels, 70% of V
Input Low Voltage (pin 1) CMOS levels, 30% of V
Input High Current (pin 1) V
Input Low Current (pin 1) V

= V

in

DD

= V

in

SS

DD
DD

0.7V
V

DD

SS

–VDDV

–0.3VDDV
––10µA
––10µA

Output Leakage Current (pin 3) Three-state output, OE = 0 –10 – 10 µA
Input Capacitance (pin 1) Pin 1, or OE – 5 7 pF
Supply Current V

= 3.3V , SSCLK = 10 to 166 MHz, C

DD

= 0, OE = V

= 25°C, First year –5 – 5 ppm

A

DD

LOAD

––50mA

AC Electrical Characteristics

[2]

Parameter Description Condition Min. Typ. Max. Unit

DC Output Duty Cycle SSCLK, Measured at V
t

R

t

F

T

CCJ1

Output Rise Time 20%–80% of V
Output Fall Time 20%–80% of V

[3]

Cycle-to-Cycle Jitter SSCLK
(Pin 3)

DD, CL
DD, CL

SSCLK ≥133 MHz, Measured at VDD/2 – 85 200 ps
25 MHz ≤ SSCLK <133 MHz, Measured at

V

/2

DD

SSCLK < 25 MHz, Measured at V

T

OE1

T

OE2

T

LOCK

Notes:

2. Guaranteed by characterization, not 100% tested.

3. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percent age, temperature , and output load. For more information, refer
to the application note, “Jitter in PLL Based Systems: Causes, Effect s, and Solutio ns” available at http: //www .cypress.com/ clock/appnotes.html, or contact your
local Cypress Field Application Engineer.

Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped

outputs (Asynchronous)

Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a

valid frequency (Asynchronous)

PLL Lock Time Time for SSCLK to reach valid frequency – – 10 ms

/2 45 50 55 %

DD

= 15 pF – – 2.7 ns
= 15 pF – – 2.7 ns

– 215 400 ps

/2 – – 1% of

DD

1/SSCK

– 150 350 ns

– 150 350 ns

s

Document #: 38-07684 Rev. *E Page 3 of 7

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